Ordering number : EN5065A
CMOS LSI
LC72358N, 72362N, 72366
Single-Chip PLL Microcontrollers
Overview
The LC72358N, LC72362N, and LC72366 are 1.33 µs
instruction execution time single-chip microcontrollers for
electronic tuning applications. These products incorporate
a high-speed locking circuit and a high-performance direct
PLL circuit that can control the local oscillator C/N
characteristics. These products have 256 or 512 bytes of
RAM and 16K, 24K or 32K bytes of program ROM on
chip, and incorporate a three-channel serial I/O interface,
a six-channel A/D converter and other interfaces.
•
•
Features
• ROM
— LC72358N: 8K steps (8191
×
16 bits)
— LC72362N: 12K steps (12287
×
16 bits)
— LC72366: 16K steps (16383
×
16 bits)
The subroutine area in both products is 4K steps
(4095
×
16 bits).
• RAM
— LC72358N, 72362N: 512
×
4 bits (banks 0 to 7)
— LC72366: 1K
×
4 bits (banks 0 to F)
• Stack: Eight levels
• Serial I/O: Three channels (8-bit 3-wire format)
There are three internal serial clocks: 12.5 kHz,
37.5 kHz and 187.5 kHz.
• External interrupts:
Two channels (the INT0 and INT1 pins)
Switching between rising and falling edge detection is
supported.
• Internal interrupts:
Three channels
— Two internal timer interrupt channels
The timers provide eight interrupt periods: 100 µs,
1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms.
— One serial I/O interrupt channel
• Multiple interrupt levels:
Four levels
Hardware priority order
INT0 pin > INT1 pin > SI/O pin > internal timer 0 >
internal timer 1
• A/D converter: Six channels (6-bit successive approx-
imation type)
• General-purpose ports
— Input ports: 10
•
•
•
•
•
•
•
•
•
— Output ports: 28
— I/O ports: 25 (These pins can be switched between
input and output in bit units.)
PLL block
— Built-in sub-charge pump for high-speed locking
— Support for dead zone control
— Built-in unlock detection circuit
— Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,
10, 12.5, 25, 30, 50 and 100 kHz
Universal counter: 20 bits
Supports frequency and period
measurement with counting periods
of 1, 4, 8 and 32 ms.
Timers: Timer interrupt periods
100 µs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms
and 250 ms
Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz,
3.0 kHz, 3.75 kHz, 4.17 kHz.
Reset: Built-in voltage detection type reset circuit
Cycle time: 1.33 µs (all instructions execute in one
cycle)
Halt mode: The microcontroller operating clock is
stopped in halt mode.
There are four types of event that clear halt
mode: interrupt requests, timer FF
overflows, key inputs, and hold pin inputs.
Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V
when only the controller
block operates)
Package: QFP80E (QIP80E)
OTP version: LC72P366
Development tools: Emulator .................RE32N
Evaluation chip.......LC72EV350
Evaluation chip board
................................EB-72EV350
This LSI can easily use CCB that is SANYO’s original bus format.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT)/62295TH (OT) No. 5065-1/13
LC72358N, 72362N, 72366
Package Dimensions
unit: mm
3174-QFP80E
[LC72358N, 72362N, 72366]
SANYO: QIP80E
Pin Assignment
No. 5065-2/13
LC72358N, 72362N, 72366
Block Diagram
No. 5065-3/13
LC72358N, 72362N, 72366
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Symbol
V
DD
max
V
IN
V
OUT
(1)
V
OUT
(2)
I
OUT
(1)
Output current
I
OUT
(2)
I
OUT
(3)
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Tstg
All input pins
J port
All output ports other than V
OUT
(1)
J port
D, E, F, G, K, L, M, N, O, P and Q ports,
EO1, EO2, EO3, SUBPD
B and C ports
Ta = –40 to +85°C
Conditions
Ratings
–0.3 to +6.5
–0.3 to V
DD
+ 0.3
–0.3 to +15
–0.3 to V
DD
+ 0.3
0 to 5
0 to 3
0 to 1
400
–40 to +85
–45 to +125
Unit
V
V
V
V
mA
mA
mA
mW
°C
°C
Allowable Operating Ranges
at Ta = –40 to +85°C, V
DD
= 3.5 to 5.5 V
Parameter
Symbol
V
DD
(1)
Supply voltage
V
DD
(2)
V
DD
(3)
V
IH
(1)
Input high level voltage
V
IH
(2)
V
IH
(3)
V
IH
(4)
V
IL
(1)
Input low level voltage
V
IL
(2)
V
IL
(3)
V
IL
(4)
f
IN
(1)
f
IN
(2)
f
IN
(3)
Input frequency
f
IN
(4)
f
IN
(5)
f
IN
(6)
f
IN
(7)
f
IN
(8)
V
IN
(1)
Input amplitude
V
IN
(2)
V
IN
(3)
Input voltage range
V
IN
(4)
Conditions
CPU and PLL operating
CPU operating
Memory retention
E, H, I, L, M and Q ports, HCTR and LCTR
(when selected for input)
F, G and K ports, LCTR (period measurement mode),
HOLD
SNS
A port
E, H, I, L, M and Q ports, HCTR and LCTR
(when selected for input)
A, F, G and K ports, LCTR (period measurement mode)
SNS
HOLD
XIN
FMIN: V
IN
(2), V
DD
(1)
FMIN: V
IN
(3), V
DD
(1)
AMIN (H): V
IN
(3), V
DD
(1)
AMIN (L): V
IN
(3), V
DD
(1)
HCTR: V
IN
(3), V
DD
(1)
LCTR: V
IN
(3), V
DD
(1)
LCTR (period measurement): V
IH
(2), V
IL
(2), V
DD
(1)
XIN
FMIN
FMIN, AMIN, HCTR, LCTR
ADI0 to ADI5
min
4.5
3.5
1.3
0.7 V
DD
0.8 V
DD
2.5
0.6 V
DD
0
0
0
0
4.0
10
10
2.0
0.5
0.4
100
1
0.5
0.10
0.07
0
4.5
typ
5.0
max
5.5
5.5
5.5
V
DD
V
DD
V
DD
V
DD
0.3 V
DD
0.2 V
DD
1.3
0.4 V
DD
5.0
150
130
40
10
12
500
20
×
10
3
1.5
1.5
1.5
V
DD
Unit
V
V
V
V
V
V
V
V
V
V
V
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Hz
Vrms
Vrms
Vrms
V
No. 5065-4/13
LC72358N, 72362N, 72366
Electrical Characteristics
for the Allowable Operating Ranges
Parameter
Symbol
I
IH
(1)
I
IH
(2)
Input high level current
XIN: V
I
= V
DD
= 5.0 V
FMIN, AMIN, HCTR, LCTR: V
I
= V
DD
= 5.0 V
A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,
HCTR, LCTR, with no pull-down resistor on A port.
V
I
= V
DD
= 5.0 V,
with the E, F, G, K, L, M and Q ports selected for input.
A port: pull-down resistor present, V
I
= V
DD
= 5.0 V
XIN: V
I
= V
SS
FMIN, AMIN, HCTR, LCTR: V
I
= V
SS
A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,
HCTR, LCTR, with no pull-down resistor on A port.
V
I
= V
SS
,
with the E, F, G, K, L, M and Q ports selected for input.
A port: pull-down resistor present
A port: pull-down resistor present, V
DD
= 5 V
F, G and K ports, LCTR (period measurement mode)
B and C ports: I
O
= –1 mA
D, E, F, G, K, L, M, N, O, P and Q ports: I
O
= –1 mA
EO1, EO2, EO3, SUBPD: I
O
= –500 µA
XOUT: I
O
= –200 µA
B and C ports: I
O
= 50 µA
D, E, F, G, K, L, M, N, O, P and Q ports: I
O
= 1 mA
EO1, EO2, EO3, SUBPD: I
O
= 500 µA
XOUT: I
O
= 200 µA
J port: I
O
= 5 mA
B, C, D, E, F, G, K, L, M, N, O, P and Q ports
EO1, EO2, EO3, SUBPD
J port
ADI0 to ADI5: V
DD
(1)
P
REJ
V
DET
R
PD
(2)
I
DD
(1)
Current drain
I
DD
(2)
I
DD
(3)
I
DD
(4)
TEST1, TEST2
V
DD
(1): f
IN
(2) = 130 MHz, Ta = 25°C
V
DD
(2): Halt mode*, Ta = 25°C (Figure 1)
V
DD
= 5.5 V, oscillator stopped, Ta = 25°C (Figure 2)
V
DD
= 2.5 V, oscillator stopped, Ta = 25°C (Figure 2)
SNS
2.7
3.0
10
12
0.45
24
(0.9)
5
1
–3.0
–100
–5.0
–1/2
75
0.1 V
DD
V
DD
– 2.0
V
DD
– 1.0
V
DD
– 1.0
V
DD
– 1.0
1.0
2.0
1.0
1.0
1.5
2.0
+3.0
+100
+5.0
+1/2
50
3.3
100
0.2 V
DD
V
DD
– 1.0
2.0
4.0
50
5.0
10
15
30
Conditions
min
2.0
4.0
typ
5.0
10
max
15
30
Unit
µA
µA
I
IH
(3)
I
IH
(4)
I
IL
(1)
I
IL
(2)
3.0
µA
µA
µA
µA
Input low level current
I
IL
(3)
Input floating voltage
Pull-down resistance
Hysteresis
V
IF
R
PD
(1)
V
H
V
OH
(1)
Output high level voltage
V
OH
(2)
V
OH
(3)
V
OH
(4)
V
OL
(1)
V
OL
(2)
Output low level voltage
V
OL
(3)
V
OL
(4)
V
OL
(5)
I
OFF
(1)
Output off leakage current
I
OFF
(2)
I
OFF
(3)
A/D conversion error
Reject pulse width
Power-down detection voltage
Pull-down resistance
3.0
µA
0.05 V
DD
200
V
kΩ
V
V
V
V
V
V
V
V
V
V
µA
nA
µA
LSB
µs
V
kΩ
mA
mA
µA
µA
Note: Execute 20 STEP instructions every 1 ms. With the PLL, counters and other functions all stopped.
( ) Value: LC72366
Test Circuit
Note: All of the pins PB to PG and PJ to PQ must be left open.
Here, the pins PE to PG, PK to PM, and PQ are selected for output.
Note: All of the pins PA to PQ must be left open.
Figure 1: I
DD
(2) in Halt Mode
Figure 2. I
DD
(3) and I
DD
(4) in Backup Mode
No. 5065-5/13
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