PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 7 — 26 September 2014
Product data sheet
1. General description
The PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI)
shift register designed to monitor the status of switch inputs. It generates an interrupt
when one or more of the switch inputs change state. The input level is recognized as a
HIGH when it is greater than 0.7
V
DD
and as a LOW when it is less than 0.4
V
DD
(minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs
and the PCA9702 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK.
Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a
series resistor (minimum 100 k), the input can connect to a 12 V battery and support
double battery, reverse battery, 27 V jump start and 40 V load dump conditions in
automotive applications. Higher voltages can be tolerated on the inputs depending on the
series resistor used to limit the input current.
With both the high breakdown voltage and high ESD, these devices are useful for both
automotive and mobile applications.
The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702
which have an interrupt masking feature allowing selected inputs to not generate
interrupts and provides higher ground offset of 0.55
V
DD
(minimum of 2.5 V at 5 V node)
with minimum hysteresis of 0.05
V
DD
(minimum of 225 mV at 5 V node).
2. Features and benefits
16 general purpose input ports (PCA9701) or 8 general purpose input ports
(PCA9702)
18 V tolerant input ports with 100 k external series resistor
Input LOW threshold 0.4
V
DD
with minimum of 2 V at V
DD
= 4.5 V
Open-drain interrupt output
Interrupt enable pin (INT_EN) disables interrupt output
V
DD
range: 2.5 V to 5.5 V
I
DD
is very low 2.5
A
maximum
SPI serial interface with speeds up to 5 MHz
ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM, and 1000 V CDM
per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Operating temperature range:
40 C
to +125
C
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
PCA9701 offered in SO24, TSSOP24 and HWQFN24 packages
PCA9702 offered in TSSOP16 package
3. Applications
Body control modules
Switch monitoring
Industrial equipment
Cellular telephones
Emergency lighting
SBC wake pin extension
4. Ordering information
Table 1.
Ordering information
Topside
marking
PCA9701D
9701
Package
Name
SO24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
Version
SOT137-1
Type number
PCA9701D
PCA9701HF
PCA9701PW
PCA9702PW
HWQFN24 plastic thermal enhanced very very thin quad flat package; SOT994-1
no leads; 24 terminals; body 4
4
0.75 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT355-1
SOT403-1
PCA9701PW TSSOP24
PCA9702
TSSOP16
4.1 Ordering options
Table 2.
Ordering options
Orderable part
number
PCA9701D,118
PCA9701HF,118
Package
SO24
Packing method
Reel 13” Q1/T1
*standard mark SMD
Minimum
Temperature range
order quantity
1000
6000
2500
2500
T
amb
=
40 C
to +125
C
T
amb
=
40 C
to +125
C
T
amb
=
40 C
to +125
C
T
amb
=
40 C
to +125
C
Type number
PCA9701D
PCA9701HF
PCA9701PW
PCA9702PW
HWQFN24 Reel 13” Q1/T1
*standard mark SMD
Reel 13” Q1/T1
*standard mark SMD
Reel 13” Q1/T1
*standard mark SMD
PCA9701PW,118 TSSOP24
PCA9702PW,118 TSSOP16
PCA9701_PCA9702
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 26 September 2014
2 of 29
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
5. Block diagram
V
DD
PCA9701/PCA9702
INT
IN0
DFF0
INT_EN
IN1
DFF1
SHIFT
REGISTER
INn
(1)
DFFn
(1)
INPUT
STATUS
REGISTER
SDOUT
SDIN
SCLK
CS
20
μA
V
SS
002aac422
(1) n = 15 for PCA9701; n = 7 for PCA9702
Fig 1.
Block diagram of PCA9701; PCA9702
PCA9701_PCA9702
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 26 September 2014
3 of 29
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6. Pinning information
6.1 Pinning
SDOUT
INT
INT_EN
IN0
IN1
IN2
IN3
IN4
IN5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDIN
22 SCLK
21 CS
20 IN15
19 IN14
18 IN13
17 IN12
16 IN11
15 IN10
14 IN9
13 IN8
002aac636
SDOUT
INT
INT_EN
IN0
IN1
IN2
IN3
IN4
IN5
1
2
3
4
5
6
7
8
9
24
V
DD
23
SDIN
22
SCLK
21
CS
20
IN15
19
IN14
18
IN13
17
IN12
16
IN11
15
IN10
14
IN9
13
IN8
002aac424
PCA9701D
PCA9701PW
IN6 10
IN7 11
V
SS
12
IN6
10
IN7
11
V
SS
12
Fig 2.
Pin configuration for SO24
24 INT_EN
22 SDOUT
Fig 3.
Pin configuration for TSSOP24
terminal 1
index area
IN0
IN1
IN2
IN3
IN4
IN5
1
2
3
4
5
6
19 SCLK
18 CS
17 IN15
SDOUT
INT
INT_EN
IN0
IN1
IN2
IN3
002aad050
20 SDIN
21 V
DD
23 INT
1
2
3
4
5
6
7
8
002aac425
16 V
DD
15 SDIN
14 SCLK
13 CS
12 IN7
11 IN6
10 IN5
9
IN4
PCA9701HF
16 IN14
15 IN13
14 IN12
13 IN11
PCA9702PW
IN8 10
IN9 11
IN10 12
7
8
IN7
V
SS
IN6
9
V
SS
Transparent top view
Fig 4.
Pin configuration for HWQFN24
Fig 5.
Pin configuration for TSSOP16
PCA9701_PCA9702
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 26 September 2014
4 of 29
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6.2 Pin description
Table 3.
Symbol
SDOUT
INT
INT_EN
Pin description
Pin
SO24, TSSOP24
1
2
3
HWQFN24
22
23
24
TSSOP16
1
2
3
output
output
input
3-state serial data output; normally high-impedance
open-drain interrupt output (active LOW)
interrupt output enable
1 = interrupt is enabled
0 = interrupt is disabled and high-impedance
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
V
SS
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
CS
SCLK
SDIN
V
DD
[1]
Type
Description
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
4
5
6
7
9
10
11
12
8
-
-
-
-
-
-
-
-
13
14
15
16
input
input
input
input
input
input
input
input
ground
input
input
input
input
input
input
input
input
input
input
input
supply
input port 0
input port 1
input port 2
input port 3
input port 4
input port 5
input port 6
input port 7
ground supply
input port 8
input port 9
input port 10
input port 11
input port 12
input port 13
input port 14
input port 15
chip select (active LOW)
serial input clock
serial data input (20
A
pull-down)
supply voltage
HWQFN24 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
PCA9701_PCA9702
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 7 — 26 September 2014
5 of 29
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