DATASHEET
1 TO 4 CLOCK BUFFER
Description
The ICS551 is a low cost, high-speed single input to
four output clock buffer. Part of IDT’s ClockBlocks
TM
family, this is our lowest cost, small clock buffer.
See the ICS552-02B for monolithic dual version of the
ICS551 in a 20 pin QSOP.
IDT makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact IDT for all of your clocking
needs.
ICS551
Features
•
•
•
•
•
•
•
•
•
•
•
Low skew (250 ps) outputs
Pb-free packaging
Low cost clock buffer
Packaged in 8-pin SOIC
Input/Output clock frequency up to 160 MHz
Non-inverting output clock
Ideal for networking clocks
Operating Voltages of 3.3 and 5.0 V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Commercial and industrial temperature versions
Block Diagram
Q1
Q2
ICLK
Q3
Q4
Output Enable
IDT™
1 TO 4 CLOCK BUFFER
1
ICS551
REV P 051310
ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
Pin Assignment
I CLK
Q1
Q2
Q3
1
2
3
4
8
7
6
5
OE
VDD
GND
Q4
8 Pi n ( 150 mi l ) SOI C
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Input
Output
Output
Output
Output
Power
Power
Input
Clock output 1.
Clock output 2.
Clock output 3.
Clock output 4.
Connect to ground.
Pin Description
Clock input. Internal pull-up resistor.
Connect to 3.3 V or 5.0 V.
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01
µF
should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible.
A 33Ω series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
IDT™
1 TO 4 CLOCK BUFFER
2
ICS551
REV P 051310
ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS551. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
–
Max.
+85
+5.5
Units
°
C
V
IDT™
1 TO 4 CLOCK BUFFER
3
ICS551
REV P 051310
ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
DC Electrical Characteristics
VDD=3.3 V ±10%
, Ambient temperature -40 to +85
°
C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
Z
O
R
PU
C
IN
I
OS
Conditions
Note 1
Note 1
Min.
3.0
VDD/2+0.7
2
Typ.
Max.
3.6
3.8
VDD/2-0.7
VDD
0.8
Units
V
V
V
V
V
V
V
V
I
OH
= -25 mA
I
OL
= 25 mA
I
OH
= -12 mA
No load, 135 MHz
OE
OE pin
2.4
0.4
VDD-0.4
18
20
500
5
±50
mA
Ω
kΩ
pF
mA
VDD = 5 V ±10%
, Ambient temperature -40 to +85
°
C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
Z
O
R
PU
C
IN
I
OS
Conditions
Note 1
Note 1
Min.
4.5
VDD/2+1
2
Typ.
Max.
5.5
5.5
VDD/2-1
VDD
0.8
Units
V
V
V
V
V
V
V
V
I
OH
= -35 mA
I
OL
= 35 mA
I
OH
= -12 mA
No load, 135 MHz
OE
OE pin
2.4
0.4
VDD-0.4
35
20
220
5
±80
mA
Ω
kΩ
pF
mA
Notes: 1. Nominal switching threshold is VDD/2.
IDT™
1 TO 4 CLOCK BUFFER
4
ICS551
REV P 051310
ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
AC Electrical Characteristics
VDD = 3.3 V ±10%,
Ambient Temperature -40 to +85
°
C, unless stated otherwise
Parameter
Input Frequency
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
Output to Output Skew
Symbol
Conditions
15 pF load, Note 4
Min.
0
Typ.
Max. Units
160
160
1.0
1.0
MHz
MHz
ns
ns
ns
ps
t
OR
t
OF
Note 1
Note 2
0.8 to 2.0 V
2.0 to 0.8 V
135 MHz
Rising edges at VDD/2
2
4
8
250
VDD = 5 V ±10%,
Ambient Temperature -40 to +85
°
C, unless stated otherwise
Parameter
Input Frequency
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
Output to Output Skew
Notes:
1. With rail to rail input clock.
Symbol
Conditions
15 pF load, Note 4
Min.
0
Typ.
Max. Units
135
135
1.0
1.0
MHz
MHz
ns
ns
ns
ps
t
OR
t
OF
Note 1
Note 2
0.8 to 2.0 V
2.0 to 0.8 V
135 MHz
Rising edges at VDD/2
1.5
3
6
250
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock
generators.
4. With external series resistor of 33Ω positioned close to each output pin.
Marking Diagram (ICS551MLF)
8
5
Marking Diagram (ICS551MLN)
8
5
551MLF
######
YYWW
1
4
1
551MLN
######
YYWW
4
IDT™
1 TO 4 CLOCK BUFFER
5
ICS551
REV P 051310
Power technology
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