L6232E
SPINDLE DRIVER
1.5A MAXIMUM PEAK CURRENT
CONTROLLED SLEW RATE
CENTRAL CHARGE PUMP
PWM AND LINEAR MODES
CUTOFF TIME USER CONFIGURABLE
FAST, FREE-WHEELING DIODES ON CHIP
OVER-TEMPERATURE PROTECTION
BRAKE FUNCTION INPUT
DESCRIPTION
The L6232E is a triple half bridge driver intended
for use in brushless DC motor applications. This
part can be used to form the power stage of a
three-phase, brushless DC motor control loop,
and is especially useful for disk drive applications.
Power drivers are Integrated DMOS transistors
and feature fast recirculating diodes as an integral
BLOCK DIAGRAM
PLCC21+7
ORDERING NUMBER:
L6232E
part of their structure. The logic inputs are TTL-
level compatible, with internal pull-up, allowing in-
terfacing to open collector outputs. All necessary
circuitry to perform PWM and linear motor speed
control is included. A central charge pump is util-
ized to drive the upper DMOS transistors, and
also to power the braking function. The L6232E is
packaged in PLCC28.
October 1996
1/10
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6232E
PIN DESCRIPTION
Pin
1 to 4
5, 9
6
7, 11
8
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 to 28
Name
GND
SENSE
INLB
V
S
INLA
C
S
C
P
RC
INLC
BRK DLY
INUC
PWM Vref
LIN Vref
COMP
OUTA
BRK
OUTB
INUA
INUB
OUTC
GND
Output for current sense resistors.
Logic Input to turn on the lower driver (Active High).
Supply Voltage.
Logic input to turn on the lowey driver (Active High).
External Charge Pump Capacitor.
External Main Charge Pump capacitor.
Cutoff Time RC Network in PWM mode. The Resistor value is also used to define
the slew-rate in linear mode (LIN).
Logic input to turn on the lower driver (Active High).
External RC network for the brake delay.
Logic Input to turn on the upper driver (Active Low).
Input for Reference Control in PWM mode
Input for Reference Control voltage in LIN mode
External compensation for error amplifier
DMOS Half-bridge A Out.
Active LOW logic input that triggers the delayed brake.
DMOS Half-bridge B Out.
Logic Input to turn on the upper drivers (Active Low).
Logic Input to turn on the upper drivers (Active Low).
DMOS Half-bridge C Out.
Common Ground. Also provides heat-sink to PCB.
Function
Common Ground. Also provides heat-sink to PCB.
PIN CONNECTION
(Top view)
2/10
L6232E
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS sus
V
S
V
O pe ak
V
Cp
V
i
V
REF
V
is
I
p
I
O
P
tot
T
stg
, T
j
Supply Voltage
Output Peak Voltage (t
pK
= 5
µsec;
10% d.c.)
Charge Pump Input Voltage
Logic Input Voltage
PWM VREF--LIN VREF Input Voltage
Sense Input Voltage
Sink-Source Peak Output Current (*)
Sink-Source DC Output Current
Total Power Dissipation (T
amb
= 70°C)
Storage and Junction Temperature
Parameter
Peak Output Sustaining Voltage
Value
15
15
18
30
-0.3 to 7
-0.3 to 7
-1 to 7
3.5
1.8
1.5
-40 to 150
Unit
V
V
V
V
V
V
V
A
A
W
°
C
THERMAL DATA
Symbol
R
th j-pin
R
th j-amb
Description
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient (**)
Max.
Max.
Value
14
52
Unit
°C/W
°
C/W
Notes
(*) Pulse width (limited only by junction temperature and by the transient thermal resistance.
(**) Mounted on board with 16cm
2
35µm thickness copper area on board heatsink.
ELECTRICAL CHARACTERISTICS
(See the block diagram, V
S
=12V, R = 100KΩ; C = 180pF;
T
j
= 25
°
C, unless otherwise specified)
Symbol
V
S
I
S
Parameter
Supply Voltage
Quiescent Supply Current
BRK = L; INUA = INUB = INUC
= L; INLA = INLB = INLC = H;
Table 1
BRK = H; INUA = INUB = INUC
= H; INLA = INLB = INLC = L;
Table 1
I
OL
R
DSon
R
DSon
V
F
t
d(BRK)
T
BRK
I
B(LIN)
I
B(PWM)
LIN V
ref
PWM V
ref
G
v
Sense Amplifier Voltage Gain
Output Leakage Current
Sink Out ON Resistance
Source Out ON Resistance
Body Diode Forward Drop (sink
and source)
Brake Delay Time
Braking Time
LIN Vref Input Bias Current
PWM Vref Input Bias Current
Reference Voltage Input
LIN V
ref
= 0.4 to 5.5V
PWM V
ref
= 0.4 to 5.5V
Note 2; R
S
= 0.5Ω
I
motor
(PWM) = 1A
I
motor
(LIN) = 200mA
PWM V
ref
= 2.5V,
LIN V
ref
= 0.4V,
R
S
= 0.5Ω; Note 2
3.7
V
O
= V
S
= 13.5V
T
j
= 25°C (see Fig.4)
T
j
= 125
°
C
T
j
= 25
°
C (see Fig.4)
T
j
= 125°C
I
DS
= 1A (see Fig. 6)
See Fig. 1, 3; note1
10
400
400
2
0.4
4
4.3
950
950
0.42
0.7
0.42
0.7
1
210
1.5
0.47
Test Condition
Min.
10.5
Typ.
12
0.3
Max.
13.5
0.5
Unit
V
mA
4
6
mA
1
0.47
mA
Ω
Ω
Ω
Ω
V
ms
s
nA
nA
V
V
V/V
3/10
L6232E
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
G
m
Zout
V
INH
V
INL
I
INH(leak)
I
INL
t
donU
t
donL
t
doffU
t
doffL
dV/dt
dV/dt
dV/dt
F
C
T
off
T
sd
T
sdr
Notes:
1) The Head Park time must be shorter than the Brake Delay time t
d(BRK)
= R
d
C
d
2) Both in PWM and in LIN mode the Ref. Voltage must agree to V
ref
=G
V
R
S
I
motor
3) The resistance of the RC network defines the dv/dt value.
4) t
off
= 1.8RC + 6
⋅
10
-6
Parameter
LIN Error Amplifier
Transconductance
Error Amplifier Output
Impedance
Logic Input Voltage BRK; INUA;
INUB; INUC; INLA; INLB; INLC
Logic Input Current BRK; INUA;
INUB; INUC; INLA; INLB; INLC
Upper/Lower Turn-on Delay
Upper/Lower Turn-off Delay
Source DMOS Slew-Rate
(PWM)
Source DMOS Slew-Rate (LIN)
Sink DMOS Output Turn-off
Slew-Rate
Internal Clock Frequency
PWM Cutoff Time
Shutdown Temperature
Recovery Temperature
Test Condition
Min.
Typ.
0.8
2
Max.
Unit
mA/V
MΩ
V
2
0.8
V
i
= 2.7V
V
i
= 0.4V
Table 1
see Fig. 3
0.7
0.15
15
0.5
see Fig. 3
see Fig. 3
Note 3; R = 100KΩ
0.15
380
R=100KΩ; C=180pF, Note 4;
see Fig. 2
40
160
120
10
1
-1
-0.1
V
mA
mA
µs
µs
µs
µ
s
V/
µ
s
V/µs
V/µs
KHz
µs
°C
°
C
Table 1
INPUT STATE
INUA
L
L
H
H
INUB
L
L
H
H
INUC
L
L
H
H
INLA
H
L
L
H
INLB
H
L
L
H
INLC
H
L
L
H
A
*
H
*
L
OUTPUT STATE
B
*
H
*
L
C
*
H
*
L
H = The Upper DMOS is ON
L = The Lower DMOS is ON
* = Tristate condition
4/10
L6232E
Figure 1:
Brake Delay and Braking timing of the L6232E. At the time t1 a VP Powerdown threshold
detector drives low the BRK input; at time t2 the Charge Pump voltage becomes inadequate
to maintain ON the lower DMOS.
FUNCTIONAL DESCRIPTION
(Refer to the
Block Diagram)
The commutation sequence is provided by the
user via six inputs. INUA,INUB,INUC turn on the
three upper DMOS drivers when held at logic
LOW, and inputs INLA,INLB,INLC turn on the
three lower DMOS drivers when held at logic
HIGH.
The BRK and BRK DLY inputs offer flexibility to
the system designer in the implementation of the
braking function. The BRK logic input, when
pulled low will turn-off all upper and lower Dmos
drivers. The low transition at BRK will produce a
delayed negative transition at the BRK DLY input,
configurable by connection of a capacitor Cd and
a resistor Rd from the BRK DLY pin to ground.
The negative transition at BRK DLY will initiate
the braking of the motor by turning on all lower
Dmos, while keeping all upper DMOS turned-off.
This feature provides a time interval where the
motor BEMF can be used to power the head
parking function before the braking procedure is
iniziated. External detection of the supply(VP)
drop-off is necessary to provide the appropriate
logic signal to the BRK input. (see Fig. 1)
The brake function utilizes the energy stored in
the central charge pump capacitor (Cp) to turn-on
or turn-off the DMOS drivers. This allows for
completion of the braking procedure after the VP
supply has powered down.
The L6232E is capable of driving the motor in
either pulse width modulation (PWM) or linear
(LIN) mode. The driving mode is determined by
the smaller of two analog voltages inputs, LIN
Vref and PWM Vref. The motor current is control-
led by LIN Vref and PWM Vref and the current
sense resistor Rs connected to the SENSE out-
put. The SENSE output provides for connection of
a resistor in series with the source of all lower
DMOS drivers. The voltage at this pin provides
the error signal wich is utilized internally to regu-
late the motor current Im. The current in both
PWM and linear mode is determined by the ex-
pression :
V
ref
I
m
=
G
V
⋅
R
S
in wich Gv is the voltage gain of the sense ampli-
fier. In linear mode, the current is regulated by a
linear control loop wich drives the lower DMOS.
Compensation of the linear control loop is
achieved by connection of a series network
(Rc,Cc) from the transconductance amplifier out-
put (Gm) and ground. Control is passed to each
lower DMOS in succession during the commuta-
tion sequence(MPX).
The rate at which the upper and lower drivers
turns-off during linear mode operation is configur-
able externally by the value of the resistor R used
at the RC pin. This defines a current which is util-
ized internally to limit the voltage slew-rate at the
outputs during transitions. The output slew-rate is
internally adjusted for fast slewing during PWM
operation to reduce losses, and a relatively
slower rate during linear mode operation to mini-
5/10
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