5962-9461107HXC datasheet, PDF

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5962-9461107HXC: DescriptionCache SRAM Module, 512KX32, 35ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66; Categorystorage storage; File Size288KB，40 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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5962-9461107HXC Overview

Cache SRAM Module, 512KX32, 35ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9461107HXC Parametric

Parameter Name	Attribute value
package instruction	HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Reach Compliance Code	unknown
Maximum access time	35 ns
Other features	ALSO CONFIGURABLE AS 2M X 8
Spare memory width	16
I/O type	COMMON
JESD-30 code	S-CPGA-P66
JESD-609 code	e4
memory density	16777216 bit
Memory IC Type	CACHE SRAM MODULE
memory width	32
Number of functions	1
Number of terminals	66
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX32
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA66,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	6.223 mm
Maximum standby current	0.028 A
Minimum standby current	2 V
Maximum slew rate	0.57 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Figure 1; changed case outline M to be available in either a single or

dual cavity package. Added vendor CAGE code 0EU86 for device

types 05 through 10. -sld

Added device types 11 through 16.

Add note to paragraph 1.2.2 and table I, conditions. Add thermal

resistance, junction-to-case (θ

) for all case outlines. Add case

outline 9.

Table I, I

change maximum limits and I

change maximum limits.

Figure 1, case outline M, correct diagram adding "c" dimension, lead

thickness and change dimension A2 maximum from 0.020" to 0.025".

Figure 1, case outline 9, minimum dimension for D2/E2, change

0.990 inches to 0.980 inches and 25.15 mm to 24.89 mm.

Table I; Operating supply current (I

) changed the maximum limit for

device types 9 and 15 at f = 50 MHz from 700 mA to 725 mA and for

device types 10 and 16 at f = 58.8 MHz from 700 mA to 750 mA. -sld

Added device types 17 through 20. -sld

Added case outline A. -sld

Added case outline B. Added note to paragraph 1.2.4. -sld

Table I; Changed the I

from 8 mA to 6 mA for device types 07-10

and 13 -20 for the V

test. Editorial changes throughout. -sld

DATE (YR-MO-DA)

99-04-22

APPROVED

K. A. Cottongim

99-08-18

00-04-06

Raymond Monnin

00-06-19

Raymond Monnin

01-5-16

01-12-21

Raymond Monnin

02-11-18

03-02-24

03-12-19

04-05-03

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Gary Zahn

CHECKED BY

Michael C. Jones

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216

http://www.dscc.dla.mil

APPROVED BY

Kendall A. Cottongim

MICROCIRCUIT, HYBRID, MEMORY,

DIGITAL, 512K x 32-BIT, STATIC RANDOM

ACCESS MEMORY, CMOS

SIZE

SHEET

CAGE CODE

DRAWING APPROVAL DATE

95-11-13

REVISION LEVEL

67268

1 OF

5962-94611

5962-E251-04

DSCC FORM 2233

APR 97

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in

accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as

designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class. The

manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as

defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not

affect the form, fit, or function of the device for the applicable device class.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38534 and herein.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.

3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 and 5.

3.2.5 Block diagram. The block diagram shall be as specified on figure 6.

3.2.6 Output load circuit. The output load circuit shall be as specified on figure 7.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

as specified in table I and shall apply over the full specified operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are described in table I.

3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked

with the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked.

3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described

herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot

sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for

those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer

and be made available to the preparing activity (DSCC-VA) upon request.

3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this

drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets

the performance requirements of MIL-PRF-38534 and herein.

3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of

microcircuits delivered to this drawing.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

SIZE

REVISION LEVEL

5962-94611

SHEET

DSCC FORM 2234

APR 97

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