EEWORLDEEWORLDEEWORLD

Part Number

Search

41W-B1K28HD-CW0

Description
Single Color LED, Blue, Water Clear, 7.1mm,
CategoryLED optoelectronic/LED    photoelectric   
File Size222KB,2 Pages
ManufacturerDDP Engineered LED Solutions
Environmental Compliance
Download Datasheet Parametric View All

41W-B1K28HD-CW0 Overview

Single Color LED, Blue, Water Clear, 7.1mm,

41W-B1K28HD-CW0 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codeunknown
colorBLUE
ConfigurationSINGLE WITH BUILT-IN DIODE
Maximum forward current0.03 A
Lens typeWATER CLEAR
Nominal luminous intensity1000 mcd
Installation featuresRADIAL MOUNT
Number of functions1
Number of terminals2
Maximum operating temperature80 °C
Minimum operating temperature-20 °C
Optoelectronic device typesSINGLE COLOR LED
total height23.27 mm
method of packingBULK
peak wavelength465 nm
shapeCYLINDRICAL
size7.1 mm
surface mountNO
Terminal pitch4.2 mm
Base Number Matches1
Please give me a PWM program
DSP2812 generates 4-channel PWM wave with dead zone delay to control the forward and reverse rotation of the motor...
zeroD0 Microcontroller MCU
2010 latest products for the interior industry, check out other people's information
Latest products for the industry...
安_然 Test/Measurement
What could be wrong if the PWM output program of stm32f103c8t6 cannot be adjusted?
The 2-channel of TIM4 of stm32f103c8t6 outputs PWM. The corresponding port of this channel is B7. A small light is connected to B7. I want to observe whether the PWM is output correctly by the status ...
shijizai stm32/stm8
If you are familiar with SQL Server Compact Edition, please enter
I am now using SQL Server Compact Edition to create a mobile application. When creating a new subscription for the SQL Server Compact Edition database, an error occurs. I don't know what went wrong. P...
zlp520 Embedded System
Problems with FPGA-based stereo matching
I am in my second year of graduate school and am about to start a project to implement stereo matching of two images using FPGA. As a beginner in FPGA, I don't know how to do it? What knowledge of FPG...
yuechenping FPGA/CPLD
Timing constraint problem
I have no way to constrain the clock. This is what happens. I commented out the automatically generated one, but it still doesn't work. Ignored create_clock: Incorrect assignment for clock. Source nod...
3008202060 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2330  1762  1880  439  1237  47  36  38  9  25 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号