KM68512A Family
Document Title
64Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
0.1
1.0
2.0
History
Initial draft
Revision
Finalize
Revision
- Add 45ns part with 30pf test load.
Revision
- Change Data Sheet format :
One data sheets for industrial and commercial product
Revision
- Change Data Sheet format
- Remove 45ns part from commercial product and 100ns part
from industrial product
- Remove low power part form TSOP package
Draft Data
Novemer 28, 1993
May 13, 1994
December 1, 1994
August 12, 1995
Remark
Design target
Preliminary
Final
Final
3.0
April 15, 1996
Final
4.0
January 9, 1998
Final
The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 4.0
January 1997
KM68512A Family
64Kx8 bit Low Power CMOS Static RAM
FEATURES
•
Process Technology: Poly Load
•
Organization: 64Kx8
•
Power Supply Voltage: 4.5~5.5V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-SOP-525, 32-TSOP1-0820F
CMOS SRAM
GENERAL DESCRIPTION
The KM68512A families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
KM68512AL
KM68512AL-L
KM68512ALI
KM68512ALI-L
Industrial (-40~85°C)
Operating Temperature
V
CC
Range
Speed
Standby
(I
SB1
, Max)
100µA
20µA
70ns
100µA
50µA
70mA
32-SOP
32-TSOP1-F
Operating
(I
CC2
, Max)
PKG Type
Commercial (0~70°C)
4.5 to 5.5V
55/70ns
PIN DESCRIPTION
N.C
N.C
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A3
A4
A5
A6
A7
A12
A13
A14
A15
32-SOP
25
24
23
22
21
20
19
18
17
Row
select
32-TSOP
Type1 - Forward
Memory array
512 rows
128×8 columns
I/O1
I/O8
Data
cont
I/O Circuit
Column select
Data
cont
Name
CS
1
, CS
2
OE
WE
A
0
~A
15
I/O
1
~I/O
8
Vcc
Vss
N.C
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Power
Ground
No Connection
CS1
CS2
WE
OE
A0
A1
A2
A8
A9 A10 A11
Control
Logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 4.0
January 1997
KM68512A Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
KM68512ALG-5
KM68512ALG-5L
KM68512ALG-7
KM68512ALG-7L
KM68512ALT-5L
KM68512ALT-7L
Function
32-SOP, 55ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 55ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
KM68512ALTI-7L
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
KM68512ALGI-7
KM68512ALGI-7L
Function
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Ratings
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
260°C, 10sec(Lead Only)
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
KM68512A
KM68512AI
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 4.0
January 1997
KM68512A Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
Typ
5.0
0
-
-
CMOS SRAM
Max
5.5
0
Vcc+0.5V
2)
0.8
Unit
V
V
V
V
Note
1. Commercial Product : T
A
=0 to 70°C, unless otherwise specified
Industrial Product : T
A
=-40 to 85°C, unless otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby
Current
(CMOS)
KM68512AL/L-L
I
SB1
KM68512ALI/LI-L
V
OL
V
OH
I
SB
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA
CS
1
≤0.2V,
CS
2
≥V
CC
-0.2V, V
IN
≤0.2V
or V
IN
≥Vcc
-0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IH
or V
IL
Test Conditions
Min
-1
-1
-
-
-
-
2.4
-
-
-
-
-
Typ Max Unit
-
-
7
-
-
-
-
-
2
1
2
1
1
1
15
10
70
0.4
-
3
100
20
100
50
µA
µA
mA
mA
mA
V
V
mA
µA
µA
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS
2
=V
IL
,
Other inputs =V
IH
or V
IL
Low Power
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
Low Low Power
Other inputs =0 ~ Vcc
Low Power
Low Low Power
4
Revision 4.0
January 1997
KM68512A Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
CMOS SRAM
C
L
1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Vcc=4.5~5.5V, KM68512A Family:T
A
=0 to 70°C,
Parameter List
Symbol
KM68512AI Family:T
A
=-40 to 85°C)
Speed Bins
55ns
70ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
V
DR
KM68512AL/L-L
Data retention current
I
DR
KM68512ALI/LI-L
Data retention set-up time
Recovery time
t
SDR
t
RDR
Symbol
Test Condition
CS
1
1)
≥Vcc-0.2V
Vcc=3.0V CS
1
≥Vcc-0.2V
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
Min
2.0
-
-
-
-
0
5
Typ
-
1
0.5
-
-
-
-
Max
5.5
50
10
50
25
-
-
Unit
V
µA
See data retention waveform
ms
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(
CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled).
5
Revision 4.0
January 1997
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