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597GA000583DG

Description
Programmable Oscillators VCXO (NCNR)
CategoryPassive components   
File Size320KB,12 Pages
ManufacturerSilicon Laboratories
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597GA000583DG Overview

Programmable Oscillators VCXO (NCNR)

597GA000583DG Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerSilicon Laboratories
Product CategoryProgrammable Oscillators
RoHSDetails
ProductVCXO
Package / Case7 mm x 5 mm
Length7 mm
Width5 mm
Factory Pack Quantity1
Unit Weight0.006562 oz
Si597
Q
UAD
F
R E Q U E N C Y
V
O L TAG E
- C
O N T R O L L E D
C
RYSTAL
O
SCILLATOR
( V C X O ) 1 0
TO
810 MH
Z
Features
Available with any-frequency
output from 10 to 810 MHz
4 selectable output frequencies
3rd generation DSPLL
®
with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
Si5602
Applications
Ordering Information:
See page 7.
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
OTN
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Description
The Si597 quad frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low-jitter clock for all output frequencies. The
Si597 is available with one of four pin-selectable ouput frequencies from 10
to 810 MHz. Unlike traditional VCXOs, where a different crystal is required
for each output frequency, the Si597 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides supply noise rejection, simplifying
the task of generating low-jitter clocks in noisy environments. The Si597 IC-
based quad frequency VCXO is factory-configurable for a wide variety of
user specifications including frequencies, supply voltage, output format,
tuning slope, and absolute pull range (APR). Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
FS[1]
7
V
C
1
6
V
DD
OE
2
5
CLK–
GND
3
8
FS[0]
4
CLK+
Functional Block Diagram
V
DD
P oo w e r S u p p ly F ilte rin g
P w e r S u p p ly F ilte rin g
OE
CLK+
F ixe d
F re q u e n cy
O s cilla to r
A n y F re q u e n c y
10–810 M H z
DSPLL
C lo c k S y n th e s is
CLK-
V
c
ADC
C o n tro l
GND
FS0
FS1
Rev. 1.0 12/11
Copyright © 2011 by Silicon Laboratories
Si597
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