AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
Features
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Single chip USB to 10/100/1000 Gigabit Ethernet
and HomePNA and HomePlug Network Controller
USB specification 1.0 and 1.1 and 2.0 compliant
Supports USB Full and High Speed modes with
Bus power capability
Supports 4 endpoints on USB interface
High performance packet transfer rate over USB
bus using proprietary burst transfer mechanism
(submitted for US patent application)
IEEE 802.3, 802.3u, and 802.3ab (10BASE-T,
100BASE-TX, and 1000BASE-T) compatible
Embedded 20KB SRAM for RX packet buffering
and 20KB SRAM for TX packet buffering
Supports both full-duplex and half-duplex
operation in Fast Ethernet
Provides MII/GMII/RGMII interfaces for Ethernet
PHY interface and MII interface for HomePNA/
HomePlug PHY interface
Supports Jumbo packet of up to 9KB
Document No: AX88178-02/4/20/2004
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Supports Suspend mode and Remote Wakeup via
Link-up, Magic packet, or external pin
Optional PHY power down during Suspend mode
Supports 256/512 bytes (93c56/93c66) of serial
EEPROM (for storing USB Descriptors)
Supports automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM after power-on initialization
External PHY loop-back diagnostic capability
Integrates on-chip 3.3V to 2.5V voltage regulator
and requires only single power supply: 3.3V
Small form factor with 128-pin LQFP package
12MHz clock input from either crystal or oscillator
source
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product Description
The AX88178 USB to 10/100/1000 Gigabit Ethernet/HomePNA/HomePlug controller is a high performance and highly
integrated ASIC with embedded 40KB SRAM for packet buffering. It enables low cost and affordable Gigabit Ethernet
network connection to desktop and notebook PC using popular USB ports that are built-in to many PC today. It has an
USB interface to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It
implements 10/100/1000Mbps Ethernet LAN function based on IEEE802.3, IEEE802.3u, IEEE802.3ab standards or
HomePNA standard. It supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet
and HomePNA functions. It also provides gigabit media-independent (GMII) and reduced gigabit media-independent
(RGMII) interface for interfacing with Gigabit Ethernet PHY.
System Block Diagram
RJ45
Magnetic
10/100/1000 Gigabit Ethernet PHY
RJ11
Magnetic
1/10 Mbps Home LAN PHY
AX88178
USB I/F
EEPROM
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
FAX: 886-3-579-9558
TEL: 886-3-579-9500
Released Date: 4/16/2004
http://www.asix.com.tw
AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
INTRODUCTION .....................................................................................................3
SIGNAL DESCRIPTION..........................................................................................5
FUNCTION DESCRIPTION .....................................................................................8
SERIAL EEPROM MEMORY MAP .........................................................................9
USB CONFIGURATION STRUCTURE .................................................................13
USB COMMANDS.................................................................................................14
ELECTRICAL SPECIFICATIONS .........................................................................25
PACKAGE INFORMATION...................................................................................32
ORDERING INFORMATION .................................................................................33
APPENDIX A: SYSTEM APPLICATIONS ........................................................................33
REVISION HISTORY.........................................................................................................35
List of Figures
F
IGURE
1: AX88178 B
LOCK
D
IAGRAM
................................................................................................3
F
IGURE
2: AX88178 P
INOUT
D
IAGRAM
................................................................................................4
F
IGURE
3: M
ULTICAST
F
ILTER
E
XAMPLE
............................................................................................20
List of Tables
T
ABLE
1: P
INOUT
D
ESCRIPTON
.............................................................................................................5
T
ABLE
2: S
ERIAL
EEPROM M
EMORY
M
AP
.........................................................................................9
T
ABLE
3: USB S
TANDARD
C
OMMAND
R
EGISTER
M
AP
.......................................................................14
T
ABLE
4: USB V
ENDOR
C
OMMAND
R
EGISTER
M
AP
..........................................................................15
T
ABLE
5: R
EMOTE
W
AKEUP
T
RUTH
T
ABLE
........................................................................................24
2
ASIX ELECTRONICS CORPORATION
AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
1.0 Introduction
1.1 General Description
The AX88178 USB to 10/100/1000 Gigabit Ethernet/HomePNA/HomePlug controller is a high performance and highly
integrated ASIC with embedded 40KB SRAM for packet buffering. It enables low cost and affordable Gigabit Ethernet
network connection to desktop and notebook PC using popular USB ports that are built-in to many PC today. It has an
USB interface to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It
implements 10/100/1000Mbps Ethernet LAN function based on IEEE802.3, IEEE802.3u, IEEE802.3ab standards or
HomePNA standard. It supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet
and HomePNA functions. It also provides gigabit media-independent (GMII) and reduced gigabit media-independent
(RGMII) interface for interfacing with Gigabit Ethernet PHY.
The AX88178 needs 12MHz clock for USB operation and 125MHz clock for Gigabit Ethernet operation. It is in 128-pin
LQFP low profile package with CMOS process and requires only single 3.3V power supply to operate.
1.2 AX88178 Block Diagram
40KB
SRAM
Memory Arbiter
Gigabit
MAC
Core
MII/GMII/RGMII
I/F
EECS
EECK
EEDI
EEDO
GPIO2~0
SEEPROM
Loader I/F
General
Purpose I/O
USB to
Ethernet
Bridge
STA
MDC
MDIO
USB Core and Interface
DP/DM
DPRS/DMRS
Figure 1: AX88178 Block Diagram
3
ASIX ELECTRONICS CORPORATION
AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
1.3 AX88178 Pinout Diagram
The AX88178 is housed in the 128-pin LQFP package.
DB
DB
AVDDK
AGND
AGND
AVDDK
AGND
AGND
NC
NC
NC
NC
NC
NC
VDDK
GND
GND
TXD7
TXD6
TXD6
TXD5
TXD4
VDD2
VDD2
GND
TXD3
TXD3
TXD2
TXD1
TXD1
TXD0
VDD2
VDD2
GND
TX_ER
TX_ER
TX_EN
TXC
TXC
GTX_CLK
NC
NC
NC
NC
NC
NC
NC
96
95
94
93
92
91
90
89
88 87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 31
32
VDD3
GND
VDDK
GND
XIN125M
TX_CLK
RGMII_EN
RX_CLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
MDINT
VDDK
GND
MDIO
MDC
PHYRST_N
VDD2
GND
LED
USB_SPEED_LED
GND
VDD3
AVDDK
AGND
NC
NC
AGND
NC
NC
AVDDK
NC
AGND
AGND
AVDDK
NC
NC
AGND
AVDDK
NC
NC
CLKSEL
CLK60EXT
SCAN_ENABLE
SCAN_TEST
HS_TEST_MODE
VDD3
GND
AVDD3
AGND
AVDD3
DPRS
DMRS
RPU
AGND
ASIX
AX88178
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DP
DP
DM
RREF
RREF
AGND
AVDD3
AVDD3
XOUT12M
XIN12M
XIN12M
GND
VDDK
VDDK
GNDAH
VDDAH
VDDAH
V25
INT_REGULATOR_EN
VDD3
VDD3
GND
GND
GND
VDDK
FORCEFS_N
FORCEFS_N
NC
TESTSPEEDUP
TESTSPEEDUP
RESET_N
EXTWAKEUP_N
EXTWAKEUP_N
VBUS
EEDO
EEDO
VDD3
GND
GND
EEDI
EEDI
EECS
EECK
EECK
GPIO0
GPIO1
GPIO1
GPIO2
Figure 2: AX88178 Pinout Diagram
4
ASIX ELECTRONICS CORPORATION
AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
2.0 Signal Description
The following abbreviations apply to the following pin description table.
I2
I3
I5
O2
O3
O5
B
Input, 2.5V with 3.3V tolerant
Input, 3.3V
Input, 3.3V with 5V tolerant
Output, 2.5V with 3.3V tolerant
Output, 3.3V
Output, 3.3V with 5V tolerant
Bi-directional I/O
B2
B5
PU
PD
P
S
Bi-directional I/O, 2.5V with 3.3V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
Internal Pull Up (75K)
Internal Pull Down (75K)
Power Pin
Schmitt Trigger
Table 1: Pinout Descripton
Pin Name
DP
DM
DPRS
DMRS
VBUS
XIN12M
XOUT12M
RREF
RPU
Type
Pin No
Pin Description
USB Interface
B
32
USB 2.0 data positive pin.
B
31
USB 2.0 data negative pin.
B
36
USB 1.1 data positive pin. Please connect to DP through a 39ohm
(+/-1%) serial resistor.
B
35
USB 1.1 data negative pin. Please connect to DM through a 39ohm
(+/-1%) serial resistor.
I5/PD/S
10
VBUS pin input. Please connect to USB bus power.
I3
26
12Mhz crystal or oscillator clock input. This clock is needed for USB
PHY transceiver to operate.
O3
27
12Mhz crystal or oscillator clock output.
I
30
For USB PHY’s internal biasing. Please connect to AGND through a
12.1Kohm (+/-1%) resistor.
I
34
For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V)
through a 1.5Kohm (+/-5%) resistor.
Station Management Interface
O2
121
Station Management Data Clock output. The timing reference for
MDIO. All data transfers on MDIO are synchronized to the rising edge
of this clock. The frequency of MDC is 1.5MHz.
B2/PU
120
Station Management Data Input/Output. Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII spec.
I2/PU
117
Station Management Interrupt input.
MII/GMII/RGMII Interface
I2
104
Receive Clock. RX_CLK is received from PHY to provide timing
reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals
on receive direction of MII/GMII/RGMII interface.
I2
114, 113, Receive Data. RXD [7:0] is driven synchronously with respect to
112, 111, RX_CLK by PHY. In RGMII mode, only RXD [3:0] is used.
110, 109,
108, 107
I2
105
Receive Data Valid. RX_DV is driven synchronously with respect to
RX_CLK by PHY. It is asserted high when valid data is present on
RXD [7:0]. In RGMII mode, RX_DV acts as RX_CTL.
I2
106
Receive Error. RX_ER is driven synchronously with respect to
RX_CLK by PHY. It is asserted high for one or more RX_CLK
periods to indicate to the MAC that an error has detected.
I2
116
Collision Detected. COL is driven high by PHY when the collision is
detected.
I2
115
Carrier Sense. CRS is asserted high asynchronously by the PHY when
either transmit or receive medium is non-idle.
5
ASIX ELECTRONICS CORPORATION
MDC
MDIO
MDINT
RX_CLK
RXD [7:0]
RX_DV
RX_ER
COL
CRS
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