SDRAM 256Mb E-die (x4, x8
x8)
CMOS SDRAM
256Mb E-die SDRAM Specification
54pin sTSOP-II
Revision 1.1
February. 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February, 2004
SDRAM 256Mb E-die (x4, x8
x8)
Revision History
Revision 1.0 (August. 2003)
- First release.
Revision 1.1 (February. 2004)
- Deleted x16 for data book.
CMOS SDRAM
Rev. 1.1 February, 2004
SDRAM 256Mb E-die (x4, x8
x8)
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8)
• Auto & self refresh
• 64ms refresh period (8K Cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S560432E / K4S560832E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by
4bits / 4 x 8,388,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows pre-
cise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro-
grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
Ordering Information
Part No.
K4S560432E-NC(L)75
K4S560832E-NC(L)75
Orgainization
64M x 4
32M x 8
Max Freq.
133MHz
133MHz
Interface
LVTTL
LVTTL
Package
54pin sTSOP
54pin sTSOP
Organization
64Mx4
32Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
Row & Column address configuration
Rev. 1.1 February, 2004
SDRAM 256Mb E-die (x4, x8
x8)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
16M x 4 / 8M x 8 / 4M x 16
Sense AMP
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February, 2004
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