K4H561638D-GLB0 datasheet, PDF

Datasheet> All Categories > storage> storage> K4H561638D-GLB0

K4H561638D-GLB0: DescriptionDDR 256Mb; Categorystorage storage; File Size293KB，26 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

Download Datasheet Parametric View All

K4H561638D-GLB0 Overview

DDR 256Mb

K4H561638D-GLB0 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TBGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
JESD-609 code	e0
length	15.1 mm
memory density	268435456 bi
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.05 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.003 A
Maximum slew rate	0.3 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8.1 mm

Preview

Download Datasheet

View All

256Mb

Key Features

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• LDM,UDM/DM for write masking only

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

• 60 Ball FBGA package

DDR SDRAM

ORDERING INFORMATION

Part No.

K4H560438D-GC(L)B3

K4H560438D-GC(L)A2

K4H560438D-GC(L)B0

K4H560838D-GC(L)B3

K4H560838D-GC(L)A2

K4H560838D-GC(L)B0

K4H561638D-GC(L)B3

K4H561638D-GC(L)A2

K4H561638D-GC(L)B0

16M x 16

32M x 8

64M x 4

Org.

Max Freq.

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

SSTL2

60 ball FBGA

SSTL2

60 ball FBGA

SSTL2

60 ball FBGA

Interface

Package

Operating Frequencies

- B3(DDR333)

Speed @CL2

Speed @CL2.5

133MHz

166MHz

- A2(DDR266A)

133MHz

- B0(DDR266B)

100MHz

133MHz

*CL : Cas Latency

- 1 -

Rev. 2.2 Mar. ’03

Recommended Resources

Illustration of filtering principle of power supply filter circuit

Simple magnetizer circuit one a

Triac controlled three-phase motor circuit

LED modulation circuit

Simple PID adjustment circuit

Measurement amplifier circuit with high common-mode range

How to write an anti-collision algorithm based on NRF24LE1: As the title says, has anyone written this? Let's discuss it....; yujun_2 RF/Wirelessly

How to collect data using the DAQ function assistant of LABview: [color=#333333][font=微软雅黑][size=18px]I want to ask how to use the DAQ function assistant of LABview to collect the signal transmitted by the grating ruler and control the rotation of the stepper motor...; 小瓜子 Analog electronics

Audio interface chip MS8422N using digital audio processor, P=P replaces CS8422: Package: QFN32Product DescriptionThe MS8422N is a 24-bit, high-performance asynchronous sample rate converter that integrates a digital audio interface receiver. It supports IEC60958, S/PDIF, EIAJ CP1...; 18025319604 Analogue and Mixed Signal

[Synopsys IP Resources] Using IP interfaces to reduce HPC latency and accelerate cloud computing: IDC predicts that the Global Datasphere (the amount of data created, transmitted, and stored over the Internet each year) will more than triple to 175 zettabytes over the next five years (Figure 1). M...; arui1999 Integrated technical exchanges

When configuring the 3G module, is it necessary to configure PDP?: When configuring the 3G module, is it necessary to configure PDP? What is the PDP image for? What I see on the tree is ambiguous and I don’t quite understand it. Can you please give me some advice?...; 勇敢快乐哈 Embedded System

Recommended e-book websites for programmers: [i=s]This post was last edited by kernelkoder on 2022-3-2 03:33[/i]Lore Free ebook-can search for algorithms, many bookshttps://ebook2.lorefree.com/ Dongpo download e-bookhttp://www.uzzf.com/class/r_1...; kernelkoder Integrated technical exchanges

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components