K4H561638D-GCB3 datasheet, PDF

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K4H561638D-GCB3: DescriptionDDR 256Mb; Categorystorage storage; File Size293KB，26 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4H561638D-GCB3 Overview

DDR 256Mb

K4H561638D-GCB3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TBGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
JESD-609 code	e0
length	15.1 mm
memory density	268435456 bi
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.05 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.003 A
Maximum slew rate	0.35 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8.1 mm

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256Mb

Key Features

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• LDM,UDM/DM for write masking only

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

• 60 Ball FBGA package

DDR SDRAM

ORDERING INFORMATION

Part No.

K4H560438D-GC(L)B3

K4H560438D-GC(L)A2

K4H560438D-GC(L)B0

K4H560838D-GC(L)B3

K4H560838D-GC(L)A2

K4H560838D-GC(L)B0

K4H561638D-GC(L)B3

K4H561638D-GC(L)A2

K4H561638D-GC(L)B0

16M x 16

32M x 8

64M x 4

Org.

Max Freq.

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

SSTL2

60 ball FBGA

SSTL2

60 ball FBGA

SSTL2

60 ball FBGA

Interface

Package

Operating Frequencies

- B3(DDR333)

Speed @CL2

Speed @CL2.5

133MHz

166MHz

- A2(DDR266A)

133MHz

- B0(DDR266B)

100MHz

133MHz

*CL : Cas Latency

- 1 -

Rev. 2.2 Mar. ’03

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