DDR SDRAM 256Mb E-die (x4, x8)
DDR SDRAM
256Mb E-die DDR SDRAM Specification
60Ball FBGA (x4/x8)
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Rev. 1.3 April, 2005
DDR SDRAM 256Mb E-die (x4, x8)
256Mb E-die Revision History
Revision 1.0 (June, 2003)
- First release
Revision 1.1 (August, 2003)
- Corrected typo
Revision1.2 (October, 2004)
- Corrected typo.
Revision1.3 (April, 2005)
- Added notice and corrected typo.
DDR SDRAM
Rev. 1.3 April, 2005
DDR SDRAM 256Mb E-die (x4, x8)
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
[DQ] (x4,x8)
Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA package
DDR SDRAM
Ordering Information
Part No.
K4H560438E-GC/LB3
K4H560438E-GC/LA2
K4H560438E-GC/LB0
K4H560838E-GC/LB3
K4H560838E-GC/LA2
K4H560838E-GC/LB0
32M x 8
64M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
60 FBGA
SSTL2
60 FBGA
Interface
Package
Operating Frequencies
B3(DDR333@CL=2.5)
CL-tRCD-tRP
Speed @CL2
Speed @CL2.5
2.5-3-3
133MHz
166MHz
A2(DDR266@CL=2)
2-3-3
133MHz
133MHz
B0(DDR266@CL=2.5)
2.5-3-3
100MHz
133MHz
*CL : CAS Latency
Rev. 1.3 April, 2005
DDR SDRAM 256Mb E-die (x4, x8)
Ball Description (Bottom
View)
DDR SDRAM
64M x 4bit
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
32M x 8bit
1
2
3
7
8
9
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
Organization
64Mx4
32Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.3 April, 2005
DDR SDRAM 256Mb E-die (x4, x8)
Package Physical Dimension
( Unit : mm )
DDR SDRAM
8.00
±
0.10
0.10 Max
0.80 x 8 = 6.40
ENCAPSULANT AREA
0.80 x 4 = 3.20
1.60
9
8
7
6
5
1.60
4
3
2
1
0.80
1.00
0.50
5.50
1.00 x 11 = 11.00
A
B
C
D
14.00
±
0.10
E
14.0
±
0.10
F
G
H
0.45
±
0.05
J
K
L
M
0.50
5.50
8.0 0± 0.10
0.35
±
0.05
60 - 0.45
π
±
0.05
(0.90)
(1.80)
(0.90)
TOP VIEW
1.10± 0.10
BOTTOM VIEW
60Ball FBGA Package Dimension
Rev. 1.3 April, 2005
14.00
±
0.10