256Mb sTSOPII
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 54pin sTSOP II package
ORDERING INFORMATION
Part No.
K4H560438D-NC/LB3
K4H560438D-NC/LA2
K4H560438D-NC/LB0
K4H560438D-NC/LA0
K4H560838D-NC/LB3
K4H560838D-NC/LA2
K4H560838D-NC/LB0
K4H560838D-NC/LA0
32M x 8
64M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
SSTL2
54pin sTSOP II
SSTL2
54pin sTSOP II
Interface
Package
Operating Frequencies
- B3(DDR333)
Speed @CL2
Speed @CL2.5
DLL jitter
*CL : Cas Latency
133MHz
166MHz
±0.7ns
- A2(DDR266A)
133MHz
133MHz
±0.75ns
- B0(DDR266B)
100MHz
133MHz
±0.75ns
- A0(DDR200)
100MHz
-
±0.8ns
- 1 -
Rev.0.0 May. ’
02
256Mb sTSOPII
Input/Output Function Description
SYMBOL
CK, CK
DDR SDRAM
TYPE
Input
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
Command Inputs : RAS , CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-
ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address
inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1
define which mode register is loaded during the MODE REGISTER SET command (MRS or
EMRS).
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V
±
0.2V.
DQ Ground.
Power Supply : +2.5V
±
0.2V (device specific).
Ground.
SSTL_2 reference voltage.
CKE
Input
CS
Input
RAS, CAS , WE
LDM,(U)DM
Input
Input
BA0, BA1
A [n : 0]
Input
Input
DQ
LDQS,(U)DQS
I/O
I/O
NC
V
D D
Q
V
SS
Q
V
D D
V
SS
V
R E F
-
Supply
Supply
Supply
Supply
Input
- 5 -
Rev.0.0 May. ’
02
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