DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
V850/SA1
32-BIT SINGLE-CHIP MICROCONTROLLER
TM
DESCRIPTION
The
µ
PD70F3015B, 70F3015BY, 70F3017A, and 70F3017AY are products with on-chip flash memory. Because
the devices can be programmed by the user on-board, they are ideal for the evaluation stages of system
development, small-scale production of a variety of products, and rapid development of new products.
The V850/SA1 provides a high-level cost performance ideal for applications ranging from low-power camcorders
and other AV equipment to portable telephone equipment such as cellular phones and personal handyphone
systems (PHS).
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
V850/SA1 User's Manual Hardware:
TM
V850 Family User's Manual Architecture:
U12768E
U10243E
FEATURES
Number of instructions: 74
Minimum instruction execution time:
58.8 ns (@ 17 MHz operation with main system
clock (f
XX
))
50 ns (@ 20 MHz operation with main system
clock (f
XX
))
30.5
µ
s (@ 32.768 kHz operation with subsystem
clock (f
XT
))
General-purpose registers: 32 bits
×
32 registers
Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
Memory space:
16 MB linear address space
Memory block division function: 2 MB per block
Internal memory
•
Flash memory
128 KB (
µ
PD70F3015B, 70F3015BY)
256 KB (
µ
PD70F3017A, 70F3017AY)
•
RAM
4 KB (
µ
PD70F3015B, 70F3015BY)
8 KB (
µ
PD70F3017A, 70F3017AY)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
External bus interface: 16-bit data bus
Address bus: Separate output enabled
Interrupts and exceptions
External: 8, internal: 23, exceptions: 1
I/O lines Total: 85
Timer/counters
16-bit timer:
8-bit timer:
2 channels
4 channels
Watch timer: 1 channel
Watchdog timer: 1 channel
Serial interface (SIO)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I C bus interface (
µ
PD70F3015BY, 70F3017AY)
2
A/D converter: 12 channels
DMA controller: 3 channels
RTP: 8 bits
×
1 channel or 4 bits
×
2 channels
Power-saving functions: HALT/IDLE/STOP modes
Packages: 100-pin plastic LQFP (14
×
14 mm)
121-pin plastic FBGA (12
×
12 mm)
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14527EJ3V0DS00 (3rd edition)
Date Published July 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µ
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
APPLICATIONS
Low-power portable devices
Cellular phones, PHSs, and camcorders
ORDERING INFORMATION
Part Number
Package
100-pin plastic LQFP (fine pitch) (14 x 14 mm)
100-pin plastic LQFP (fine pitch) (14 x 14 mm)
100-pin plastic LQFP (fine-pitch) (14
×
14 mm)
121-pin plastic FBGA (12
×
12 mm)
100-pin plastic LQFP (fine-pitch) (14
×
14 mm)
121-pin plastic FBGA (12
×
12 mm)
Internal ROM
128 KB (flash memory)
128 KB (flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
µ
PD70F3015BGC-8EU
µ
PD70F3015BYGC-8EU
µ
PD70F3017AGC-8EU
µ
PD70F3017AF1-EA6
µ
PD70F3017AYGC-8EU
µ
PD70F3017AYF1-EA6
2
Data Sheet U14527EJ3V0DS
µ
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
121-pin plastic FBGA (12
×
12 mm)
µ
PD70F3017AF1-EA6
µ
PD70F3017AYF1-EA6
Top View
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N
Bottom View
N M L K J H G F E D C B A
Pin
Pin
Pin
Pin
Pin
Pin
Pin Name
Pin Name
Pin Name
Pin Name
Pin Name
Pin Name
Number
Number
Number
Number
Number
Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
P20
P15
V
SS
P13
P11
P06
P03
P00
P81
P76
P73
P72
AV
SS
P21
P14
V
SS
P12
P10
P05
P02
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
P83
P80
P75
AV
SS
AV
SS
P71
P22
P23
V
SS
P24
P07
P04
P01
P82
P77
P74
AV
SS
P70
AV
REF
V
DD
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
V
DD
V
SS
AV
DD
AV
DD
AV
DD
P25
V
DD
P30
AV
DD
P64
P65
P26
P27
P33
P63
P61
P62
P31
P32
P36
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
P60
P56
P57
P34
P37
P35
P55
P53
P54
V
PP
Note
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
BV
DD
P104
P105
RESET
V
DD
V
SS
X2
P90
P120
P93
P96
BV
SS
BV
SS
BV
SS
P106
P111
P113
V
DD
XT2
X1
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
V
SS
V
SS
P92
P95
P41
P45
P44
P107
P110
P112
V
DD
XT1
V
SS
V
SS
CLKOUT
P91
P94
P40
P42
P43
V
PP
Note
P100
P52
P50
P51
P101
P102
P103
P46
P47
Note
Connect the V
PP
pin to V
SS
in the normal operating mode.
Remarks 1.
Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic
LQFP. However, the SCL and SDA pins are provided only in the
µ
PD70F3017AY.
2.
Connect the D4 pin directly to V
SS
.
4
Data Sheet U14527EJ3V0DS
µ
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
PIN IDENTIFICATION
A1 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI11:
ASCK0, ASCK1:
ASTB:
AV
DD
:
AV
REF
:
AV
SS
:
BV
DD
:
BV
SS
:
CLKOUT:
DSTB:
HLDAK:
HLDRQ:
INTP0 to INTP6:
LBEN:
NMI:
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
P80 to P83:
P90 to P96:
Note
Address Bus
Address/Data Bus
AD Trigger Input
Analog Input
Asynchronous Serial Clock
Address Strobe
Analog V
DD
Analog Reference Voltage
Analog V
SS
Power Supply for Bus Interface
Ground for Bus Interface
Clock Output
Data Strobe
Hold Acknowledge
Hold Request
Interrupt Request From Peripherals
Lower Byte Enable
Non-maskable Interrupt Request
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
P100 to P107:
P110 to P114:
P120:
RD:
RESET:
RTP0 to RTP7:
RTPTRG:
R/W:
RXD0, RXD1:
SCK0 to SCK2:
SCL
Note
Port 10
Port 11
Port 12
Read
Reset
Real-Time Port
RTP Trigger
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
Serial Input
Serial Output
Timer Input
Timer Output
Transmit Data
Upper Byte Enable
Power Supply
Programming Power Supply
Ground
Wait
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main System Clock
Crystal for Subsystem Clock
:
:
SDA
Note
SI0 to SI2:
SO0 to SO2:
TI00, TI01, TI10, :
TI11, TI2 to TI5
TO0 to TO5:
TXD0,TXD1:
UBEN:
V
DD
:
V
PP
:
V
SS
:
WAIT:
WRH:
WRL:
X1, X2:
XT1, XT2:
Applies to the
µ
PD70F3015BY and
µ
PD70F3017AY only.
Data Sheet U14527EJ3V0DS
5