8
r.
ANALOG
L.III
DEVICES
FEATURES
8- and 10-Bit Resolution
20llS Conversion Time
Microprocessor Compatibility
Very Low Power Dissipation
Parallel and Serial Outputs
Ratiometric Operation
TTL/DTL/CMOS Logic Compatibility
CMOS Monolithic Construction
CMO
10-BitMonolithic ID Converte
A
OBS
8
GENERAL
DESCRIPTION
8
The AD7570 is a monolithic CMOS 10-bit successive approxi-
mation AID converter on a 120 by 13 5 mil chip, requiring
only an external comparator,
reference and passive clocking
components.
Ratiometric
operation is inherent, since an ex-
tremely accurate multiplying DAC is used in the feedback loop.
The AD7570 parallel output data lines and Busy line utilize
three-state logic to permit bussing with other AID output and
control lines or with other I/O interface circuitry. Two enables
are available: one controls the two MSBs; the second controls
the remaining 8 LSBs. This feature provides the control interface
for most microprocessors
which can accept only an 8-bit byte.
OLE
TE
FUNCTIONAL
DIAGRAM
OUT1
OUT2
AIN
I
I
VREF
10
,..,....--0 DB9 (MSB)
DB8
18
19
28
8
SRO
DB1
DBO (lSBI
BUSY
8
The AD7570 also provides a serial data output line to be used
in conjunction
with the serial synchronization
line. The clock
can be driven externally or, with the addition of a resistor and
a capacitor, can run internally as high as 0.6MHz allowing a
total conversion time (8 bits) of typically
201ls.
An 8-bit short
cycle control pin stops the clock after exercising 8 bits, nor-
mally used for the "J" version (8-bit resolution).
The AD7570 requires two power supplies, a +15V main supply
and a +5V (for TTL/DTL logic) to + 15V (for CMOS logic)
supply for digital circuitry. Both analog and digital grounds
are available.
The AD7570 is a monolithic device using a proprietary
CMOS
process featuring a double layer metal interconnect,
on-chip
thin-film resistor network and silicon nitride passivation
ensuring high reliability and excellent long term stability.
CaMP
STRT
ClK
SUCCESSIVE
APPROXIMATION
lOGIC
27
20
21
9
BSEN
HBEN
lBEN
- SYNC
L-221-13l-1l-6T-
220
Vcc
236
16
DGND voo
66
AGND
-l
8
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringementS of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
P.O. Box 280;
Tel:617/329-4700
Telex: 924491
Norwood,
Massachusetts 02062 U.S.
Twx: 710/394-65'
Cables: ANALOG NORWOODMA:
--
(VOO
SPECIFICATIONS
0=+15V, VCC 0=+5V,
VREF
0=:!:lOV unless otherwise
PARAMETER
I
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Temperature
ANALOG INPUTS
Coefficient
noted)
TEST CONDITIONS
-
VERSIONS
TA = +25°C
8 Bits min
10 Bits min
:!:1/2LSB max
ILSB max
0.3% Reading typ
OVER SPECIFIED
TEMP. RANGE
'
'--
8 Bits min
10 Bits min
:!:1/2LSB max
ILSB max
J
L
J, L
1.L
J, L
J, L
----------------
J, L
L
J, L
J, L
SC8 = Logic "0"
SC8 = Logic "I"
fCLK = 100kHz
See Figure 5
0
8
5ppm Reading per
0
C typ
10kQ typ
-150ppm/C
typ
10kQ typ
-I 5.9"p_n1/C- ty I' ---------------
10ppm Reading per
--------.-.----------.-------
C max
OBS
DIGITAL
INPUTS
VINL 2
VINH2
VINL2
VINH2
IINL' IINH 3
CLK Input Current
CLK
Input
Current
Analog Input Resistance
Analog Input Resistance Tempco
Reference Input Resistance
Reference Input Resistance Tempco
ANALOG OUTPUTS
Output Leakage Current
(OUT!, OUT2)
Output Capacitance OUTI
OUT2
OUT!
OUT2
5kQ Olin, 20kQ max
5kQ min, 20kQ max
1.
J, L
J, L
1.L
1.L
J, L
lUnA typ
120pF typ
40pF typ
40pF typ
120pF typ
200nA
max
Voun, 2 = OV
DBOthrough DB9 = Logic "I"
DBO through DB9 = Logic "0"
----------.-
1.L
J, L
J, L
J, L
J, L
J, L
J, L
1.L
+1.4V
+2.4V
+1.5V
+13-5V
typ, +0.8V max
min, + 1.4V typ
max
min
+0_8V max
+2.4V
Olin
+ 1.5V max
+ 13.5V min
Vcc = +5V
Vcc = +15V
I
:!:O_IIlA typ, :!:IOIlA max
+0.4011\ typ, +lmA max
typ,
+3mA
max
+1.7m1\
CLK Input Current
:!:IIlA typ
Cm
u
J, L
---.
2pF typ
DIGITAL
VOUTL
YOUTH
VOUTL
YOUTH
OUTPUTS
CoUT (Floating)
(SYNC, SRO,
DBO thro~gh
-
BUSY,
DB9)
J, L
1.L
1.L
J, L
J, L
and
+0.5V max
+2.4V min
+1.5V max
+13.5V min
5pF typ
OLE
TE
VIN = 0 to VCC
During Conversion Vcc = +5V;
2_4V « VIN « Vcc
During Conversion VCC = +15V;
10V « VIN « VCC
Vcc = +5V to +15V
Conversion Complete or CLK IN
« VINL
+0_8V max
+2.4V
+1.5V
min
max
+13.5V
min
I
ILKG (Floating)
(SYNC, SRO, BUSY and
DBO through DB9)
:!:5nA typ
Vcc = +5V, ISINK = 1.6mA
VCC = +5V, IsOURCE =
40llA
VCC = +15V, ISINK = 3mA
VCC = +15V, ISOURCE = ImA
VCC = +5V to +15V
SRO and SYNC; Conversion
Complete
BUSY; BSEN
=
Logic "0"
DBO-DB9; HBEN, LBEN =
Logic "0"
VCC = +5V to +15V
SRO and SYNC; Conversion
Complete
BUSY; BSEN
=
Logic "0"
DBO-DB9; HBEN, LBEN =
Logic "0"
VOUT = OV and VCC
t
DYNAMIC PERFORMANCE
Conversion Time
Internal CLK Frequency
(See Figure 2, and Section 6
of Pin Function Description)
LBEN, HBEN Propagation
tON
IoFF
Delay
J
L
J, L
1.L
20lls
typ,
40lls
max
40lls
typ, 120lls max
100kHz typ
100kHz typ
40lls
max
See Figure 5
Vcc = +5V; CLK Duty Cycle =
50%, R = 33k, C = 760pF
VCC = +15V, CLK Duty Cycle =
50%, R
=
lOk; C
=
2500pF
Vcc = +5V
LBEN, HBEN = OV to +3V
Data Bit Load = 5k, 16pF
Measured from 50% of Enable
Input to 50% Point of Data
Bit Output
Vcc = +5V
BSEN = OV to +3V
BUSY Load = 5k, 16pF
Measured from 50% Point of
BSEN Input Waveform to 50%
Point of BUSY Output Waveform
120llS max
J, L
1.L
650ns typ
200ns typ
BSEN Propagation
tON
tOFF
Delay
J, L
1.L
450ns typ
200ns ryp
Convert
Pulse
Start
Duration
(STRT)4
Requirement
,
'
-~
J, L
0.51ls
Olin
~
.-
"
-2-
--
W
i
-
----------
8
- ------
VDD
VCC
IDD
PARAMETER
I
VERSIONS
TA
~ +25°C
OVER SPECIFIED
TEMP_RANGE
TEST CONDITIONS
See Figures 3 and 4
POWER SUPPLIES
J. L
J. L
J. L
J. L
J, L
+5V to +15V typ
+5V to VDD typ
0.2mA typo 2mA max
VDD
~
+15V,
Continuous
Cycle)
fCLK ~ 0 to 100kHz
Conversion
(80% Duty
Icc
0.02mA typ, 2mA max
VCC ~ +5V. fcLK ~ 0 to 100kHz
Continuous
Conversion
(80% Duty
Cycle)
VCC = +15V,
Continuous
Cycle)
fcLK = 0 to 100kHz
Conversion
(80% Duty
O_lmA typ, 2mA max
2
..
OBS
Specifications
subject to change without notice.
, "J" version parameters specified for SC8
~
O.
VJNL and VJNH specifications applicable to all digital inputs except COMP. COMP terminal must be driven with CMOS levels (i.e., comparator
output pullup must be tied to VCc).
'IJNL,IJNH specifications not applicable to CLK terminal. See "CLK input current" in specifications table.
. STRT falling edge should not coincide with CLK in falling edge.
8
ABSOLUTE
MAXIMUM
RATINGS
8
VootoGND
VcctoGND
VcctoVOO"""""""""""""'"
VREFtoGND
AnaloglnputtoGND
Digital Input Voltage
'oUTl,'oUTZ
Power Dissipation
upto+50°c
Range.
. . . . . . . . . . . . . VOO to GND
O.3V,VoO
(package)
Derate above +50°C by. - . . . . . . . . . . . . . . . . . . IOmW/C
Operating Temperature.
. . . . . . . . . . . . . . . -25°C to +85°C
Storage Temperature.
. . . . . . . . . . . . . . .
-65°C to +150°C
OLE
TE
ORDERING INFORMATION
+17V
+17V
+OAV
:t25V
:t25V
Resolution
8-Bit
Temperature
-25°C
Range
----
to +85°C
AD7570j
la-Bit
AD7570L
Suffix D:
Ceramic
Package
IOOOmW
PIN CONFIGURATION
TOP VIEW
VDD
1.
2a
27
26
25
24
23
22
21
20
rmw
BSEN
8
CAUTION:
1. Do not
apply
voltages
higher
than
V
cc
or less than
VREF
AIN
oun
OUT2
AGND
COMP
SAD
SYNC
STAT
ClK
DGND
Vcc
lBEN
HBEN
DBa IlSB)
DBI
DB2
DB3
DB4
GND to any input/output
or AIN.
terminal
except
VREF
2. The digital control inputs are zener protected; however
permanent
damage may occur on unconnected
units
under high energy electrostatic
fields. Keep unused
units in conductive foam at all times.
3. Vcc should never exceed Voo by more than
OAV,
especially during power ON or OFF sequencing.
(MSB)
B9
D
DBa
DB7
DB6
DB5
10
11
12
19
18
17
16
15
8
-
-3-
TYPICAL PERFORMANCE CHARACTERISTICS
1000.0
VDD : +15V
CLK IN : 0 TO +3V (VCC : +5VI,
0 TO +15V IVcc : +15VI
CONVERSION.TO.STANDBY DUTY CYCLE:
100,0
HBEN, LBEN, BSEN, COMP,
SClf.
:
+0.25
+0.20
80%
>-
+0.15
AD7570J
+0,10
Vcc
t
~
~
.y
0
_0
~
10.0
;::. +0.05
~'jj
0'"
z=
0
<!~
~', -0.05
}AD7570L
~
~
-0.10
-0,15
.0.20
1.0
is
0.1
100
lk
10k
lOOk
-0,25
5
10
11
12
13
14
15
OBS
Figure
"
IDD, Ice vs. fCLK at Different
1M
lOOk 1---,-
CLOCK FREOUENCY - H,
VDD - VOL TS
Temperatures
Figure
3,
Differential
Nonlinearity
vs.
VDD
0.35
:I:
,
~
u
VDD: +15V
TA:25C
Vcc
R
10k
~
C
GENERATING
~
~
[
II
22
24
AD7570
INTERNAL CLK
lk
10
100
CAPACITANCE
-
lk
pF
OLE
TE
0.30
8
~
."
0.25
~
" 0.20
0:
,
0
0:
0:
w
z
0.15
~
0.10
8
0.05
0.00
10k
5
10
11
12
13
14
15
VDD
-
VOL TS
Figure
2.
fCLK vs. Rand
Cat
Vce =
+5V, +15V
Figure
4,
Gain Error vs. VDD (Normalized
for VDD
=
15V)
TEST CIRCUITS
-10V
+5V
SW.l
0 TO .10V
+15V
8
3k
I (MSBI
I BIT 10
BIT 11
BIT 12
(LSBI
--
BIT 1
~3
12 BIT
DAC
-
LBEN
I
21
HBEN
BSEN
27
1M
10 BIT
TEST
250k
8 BIT
TEST
10.BIT,
TEST
DUT 23
sc8126
AD7570
7
161 DB3
20
rv
ANALOG DITHER INPUT
5-40 H, SINE WAVE.
lOV P1'
100kH,
CLOCK
8B'J1,
TESV
..9:.!i
STRT
OSCILLOSCOPE
18
24
25
19
D80 (LSB)
10 BIT TEST
CONVERT START
0.5", PULSE DN 130", INTERVALS. TRAILING
EDGE SYNCED TO CLOCK LEADING EDGEI
28 I BUSY
20k
HORIZONTAL
(X) INPUT
NOTE, ADJUST COMPARATOR
6
-4-
01
02
VERTICAL
(YI INPUT
10k
DUAL "D"
TYPE LATCH
e
III
IAD311 I OFFSET TO LESS THAN
O1mV.
Figure
5.
Dynamic Crossplot Accuracy Test
8
PIN FUNCTION
INPUT CONTROLS
DESCRIPTION
1. Convert Start (pin 25 - STRT)
When the start inpu t goes to Logical" 1 ", the MS B data
latch is set to Logic "1" and all other data latches are set to
Logic "0". When the start input returns low, the conversion
sequence begins. The start command must remain high for
at least 500 nanoseconds.
If a start command is reinitiated
during
conversion,
the conversion
sequence
starts over.
2. High Byte Enable (pin 20 - HBEN)
This is a three-state enable for the bit 9 (MSB) and bit 8.
When the control is low, the output data lines for bits
9 and 8 are floating. When the control is high, digital
data from the latches appears on the data lines.
bits 0 (LSB)
8. Vcc (pin 22)
Vcc is the logic power supply. If +5V is used, all control
inputs/outputs (with the exception of comparator terminal)
are DTL/TTL compatible. If +15V is applied, control
inputs/outputs are CMOS compatible.
OUTPUT
FUNCTIONS
1. Busy (pin 28 - BUSY)
The Busy line indicates whether conversion is complete or
in process. Busy is a three-state output and floats until the
Busy-Enable line is addressed with a Logic "1 ". When
addressed, Busy will indicate either a "1" (conversion com-
plete) or a "0" (conversion in process).
~
OBS
8
<8
shows
the
internal
CLK
frequency
2. Serial Output (pin 8
-
SRO)
3. Low Byte Enable (pin 21 - LBEN)
Same as High Byte Enable pin, but controls
through 7.
4. Busy Enable (pin 27 - BSEN)
This is an interrogation
input which requests the status of
the converter, i.e., conversion in process or convert com-
plete. The converter status is addressed by applying a Logic
"1" to the Busy Enable. (See Busy under Output Functions.)
5. Short Cycle 8 Bits (pin 26 - SCS)
With a Logic "0" input, the conversion stops after 8 bits
reducing the conversion time by 2 clock periods. This
control should be exercised for proper operation of the "J"
version. When a Logic "1" is applied, a complete 10-bit con-
version takes place ("L" version).
6. Clock (pin 24 - CLK)
With an external RC connected, as shown in the figure
below, clock activity begins upon receipt of a Convert-Start
command to the A/D and ceases upon completion of con-
version. An external clock (CMOS or TTL/DTL levels) can
directly drive the clock terminals, if required. Figure 2
versus
Rand
OLE
TE
3. Serial Synchronization (pin 9
- SYNC)
Note that all digital inputs/outputs
are TTL/DTL
when Vcc is +5V, and CMOS compatible
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MNEMONIC
VDD
VREF
AIN
FUNCTION
Provides output data in serial format. Data is available only
during conversion. When the A/D is not converting, the
Serial Output line "floats." The Serial Sync (see next func-
tion)
must
be used, along with the Serial Output terminal
to avoid misinterpreting
data.
Provides 10 positive edges, which are synchronized
to the
Serial Output pin. Serial Sync is floating if conversion is
not taking place.
compatible
when VCC is +15V.
oun
OUT2
AGND
COMP
SRO
SYNC
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
HBEN
LBEN
VCC
DGND
CLK
STRT
SC8
BSEN
BUSY
C. If V
cc
~
8
is <4.75V,
the internal
CLK will not operate.
+5V
(
R
24
AD7570
CI
Generating Internal Clock Frequency
~
8
7.
VDD (pin 1)
VDD is the positive supply for all analog circuitry plus some
digital logic circuits that are not part of the TTL compatible
input/output
lines (back-gates to the P-channel devices).
Nominal supply voltage is +15V.
Positive Supply (+ 15V)
Voltage REFerence (:t10V)
Analog INput
DAC Current OUTput 1
DAC Current OUTput 2
Analog GrouND
COMParator
SeRial Output
Serial SYNChronization
Data Bit 9 (MSB)
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (LSB)
High Byte ENable
Low Byte ENable
Logic Supply (+ 5V to + 15V)
Digital GrouND
CLocK
STaRT
Short Cycle 8 Bits
BuSy ENable
BUSY
Table
1.
Function
Table
-5-
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