Dual Bootstrapped 12 V MOSFET
Driver with Output Disable
ADP3418
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
1 PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Output Disable Control Turns Off Both MOSFETs to
Float Output per Intel
®
VRM 10 Specification
APPLICATIONS
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
GENERAL DESCRIPTION
IN
FUNCTIONAL BLOCK DIAGRAM
VCC
4
BST
1
2
8 DRVH
7 SW
OVERLAP
PROTECTION
CIRCUIT
The ADP3418 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage slew
rate associated with floating high-side gate drivers. The ADP3418
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs. The
OD
pin shuts off both
the high-side and the low-side MOSFETs to prevent rapid output
capacitor discharge during system shutdown.
The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C and is available in a thermally enhanced
8-lead SOIC package.
OD
3
5 DRVL
ADP3418
6
PGND
12V
VCC
4
D1
BST
1
C
BST
CVCC
ADP3418
IN
DRVH
8
SW
7
TO INDUCTOR
DELAY
+1V
DRVL
5
1V
OD
3
6
PGND
Q2
Q1
Figure 1. General Application Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADP3418–SPECIFICATIONS
Parameter
SUPPLY
Supply Voltage Range
Supply Current
OD
INPUT
Input Voltage High
Input Voltage Low
Input Current
Propagation Delay Time
2
PWM INPUT
Input Voltage High
Input Voltage Low
Input Current
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
2
Symbol
V
CC
I
SYS
1
(VCC = 12 V, BST = 4 V to 26 V, T = 0 C to 85 C, unless otherwise noted.)
A
Conditions
Min
4.15
Typ
Max
13.2
6
Unit
V
mA
V
V
µA
ns
ns
V
V
µA
Ω
Ω
ns
ns
ns
ns
Ω
Ω
ns
ns
ns
ns
BST = 12 V, IN = 0 V
2.8
–1
3
t
pdlOD
t
pdhOD
See Figure 2
See Figure 2
3.5
–1
V
BST
– V
SW
= 12 V
V
BST
– V
SW
= 12 V
See Figure 3, V
BST
– V
SW
= 12 V,
C
LOAD
= 3 nF
See Figure 3, V
BST
– V
SW
= 12 V,
C
LOAD
= 3 nF
See Figure 3, V
BST
– V
SW
= 12 V
V
BST
– V
SW
= 12 V
15
20
0.8
+1
30
40
0.8
+1
1.8
1.0
35
20
40
20
1.8
1.0
25
21
30
10
3.0
2.5
45
30
65
35
3.0
2.5
35
30
60
20
t
rDRVH
t
fDRVH
Propagation Delay
2, 3
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
2
Propagation Delay
2, 3
t
pdhDRVH
t
pdlDRVH
t
rDRVL
t
fDRVL
t
pdhDRVL
t
pdlDRVL
See Figure 3, C
LOAD
= 3 nF
See Figure 3, C
LOAD
= 3 nF
See Figure 3
See Figure 3
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
AC specifications are guaranteed by characterization but not production tested.
3
For propagation delays, t
pdh
refers to the specified signal going high, and t
pdl
refers to it going low.
Specifications subject to change without notice.
–2–
REV. 0
ADP3418
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 15 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
SW
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +15 V
<200 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to +15 V
DRVH . . . . . . . . . . . . . . . . . . . . . . SW – 0.3 V to BST + 0.3 V
DRVL (<200 ns) . . . . . . . . . . . . . . . . . . . –2 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . . 0°C to 85°C
Operating Junction Temperature Range . . . . . . . 0°C to 150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction-to-Air Thermal Resistance (θ
JA
)
2-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
4-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
voltages are referenced to PGND.
ORDERING GUIDE
Model
ADP3418JR
Temperature Range
0°C to 85°C
Package Option
RN-8 (SOIC-8)
PIN CONFIGURATION
RN-8
BST
1
IN
2
OD
3
VCC
4
8
DRVH
SW
PGND
DRVL
ADP3418
TOP VIEW
(Not to Scale)
7
6
5
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds
this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen between
100 nF and 1
µF.
Logic Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1
µF
ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of
the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low
transition delay is determined at this pin.
Buck Drive. Output drive for the upper (buck) MOSFET.
2
3
4
5
6
7
IN
OD
VCC
DRVL
PGND
SW
8
DRVH
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3418 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADP3418
TIMING CHARACTERISTICS
OD
t
pdlOD
t
pdhOD
DRVH
OR
DRVL
90%
10%
Figure 2. Output Disable Timing Diagram
IN
t
pdlDRVL
t
fDRVL
t
pdlDRVH
t
rDRVL
DRVL
t
fDRVH
t
pdhDRVH
t
rDRVH
V
TH
DRVH-SW
V
TH
t
pdhDRVL
SW
1V
Figure 3. Nonoverlap Timing Diagram (Timing is referenced to the 90% and 10% points, unless otherwise noted.)
–4–
REV. 0
Typical Performance Characteristics–ADP3418
26
IN
1
V
CC
= 12V
C
LOAD
= 3nF
24
DRVL
FALL TIME – ns
22
DRVH
2
20
DRVH
DRVL
18
3
16
0
25
50
75
100
JUNCTION TEMPERATURE – C
125
TPC 1. DRVH Rise and DRVL Fall Times
TPC 4. DRVH and DRVL Fall Times vs. Temperature
60
IN
T
A
= 25 C
V
CC
= 12V
50
DRVH
RISE TIME – ns
DRVH
1
40
DRVL
30
2
DRVL
3
20
10
1
2
3
4
LOAD CAPACITANCE – nF
5
TPC 2. DRVH Fall and DRVL Rise Times
TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance
40
V
CC
= 12V
C
LOAD
= 3nF
DRVH
35
T
A
= 25 C
V
CC
= 12V
30
35
FALL TIME – ns
RISE TIME – ns
DRVL
25
30
DRVL
20
DRVH
25
15
20
0
25
50
75
100
JUNCTION TEMPERATURE – C
125
10
1
2
3
4
LOAD CAPACITANCE – nF
5
TPC 3. DRVH and DRVL Rise Times vs. Temperature
TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance
REV. 0
–5–
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