PI6C2305-1
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
3.3V Zero-Delay Buffer
Features
•
Zero-input-output propagation delay
•
350ps phase error
•
Multiple low-skew outputs
– Output-output skew less than 250ps
– Device-device skew less than 700ps
•
10 MHz to 100 MHz operating range
•
Low Jitter <200ps
•
High drive option (PI6C2305-1H)
•
•
•
•
3.3V operation
Commercial Operation: 0°C to +70°C
Industrial Operation: –40°C to +85°C
Package: Space-saving 8-pin, 150-mil SOIC package (W)
Description
Providing five low-skew clocks, the PI6C2305-1 is a 3.3V zero-delay
buffer designed to distribute clock signals in applications including
PC, workstation, datacom, telecom, and high-performance systems.
The PI6C2305-1 provides 5 copies of clocks that have less than
350ps propagation delay compared to a reference clock. The skew
among the output clock signals for PI6C2305-1 is less than 250ps.
When there are no rising edges on the REF input, the PI6C2305-1
enters a power-down state. In this mode, the PLL is off and all outputs
are three-stated. This results in less than 50µA of current draw.
Featuring faster rise and fall times, the PI6C2305-1H is the high-drive
version of the PI6C2305-1.
Block Diagram
Pin Configuration
REF
FBK
PLL
CLK0
CLK1
CLK2
CLK3
CLK4
REF
CLK2
CLK1
GND
1
2
3
4
8-Pin
W
8
7
6
5
CLK0
CLK4
V
DD
CLK3
Pin Description
Pin
1
2
3
4
5
6
7
8
Signal
REF
(1)
CLK2
(2)
CLK1
(2)
GND
CLK3
(2)
V
DD
CLK4
(2)
CLK0
(2)
De s cription
Input reference frequency, 5V Tolerant input
Buffered Clock output
Buffered Clock output
Ground
Buffered Clock output
3.3V Supply
Buffered Clock output
Buffered Clock output, internal feedback on this pin
Notes:
1. Weak pull-down.
2. Weak pull-down
on all outputs.
1
PS9477A
06/06/00
REF - Input to Output Clock Delay (ps)
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2305-1
3.3V Zero-Delay Buffer
Zero-Delay and Skew Control
REF. Input to CLK[1:4] Delay vs. Difference in Loading between CLK[0] pin and CLK[1:4] pins.
800
600
400
200
0
-25
-200
-20
-15
-10
-5
0
5
10
15
20
25
-400
PI6C2305-1H
-600
-800
PI6C2305-1
-900
-1000
Output Load Difference: CLK0 Load - CLK[1:4] Load (pF)
To achieve a Zero Delay between the input and output, all outputs
should be uniformly loaded. The relative loading of CLK0 (with
respect to the remaining outputs) can adjust the input-output delay.
This is shown in the graph above.
For applications requiring zero input-output delay, all outputs
including CLK0 should be equally loaded. Even if CLK0 is not used,
it must have a capacitive load that is equal to that on every other
output. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the feedback
output and remaining outputs.
Maximum Ratings
Supply Voltage to Ground Potential .................–0.5V to +7.0V
DC Input Voltage (Except REF) ............... –0.5V to V
DD
+0.5V
DC Input Voltage REF .............................................. –0.5 to 7V
Storage Temperature ..................................... –65º C to +150ºC
Maximum Soldering Temperature (10 seconds) .............. 260ºC
Junction Temperature ..................................................... 150ºC
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ................................ >2000V
2
PS9477A
06/06/00
Electrical Characteristics
(Over operating conditions)
Parame te r
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
De s cription
Input LOW Voltage
(3)
Input HIGH Voltage
(3)
Input LOW Current
Input HIGH Current
Output LOW Voltage
(4)
Output HIGH Voltage
(4)
Power Down Supply Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (2305- 1)
I
OL
= 12mA (2305- 1H)
I
OH
= –8mA (2305- 1)
I
OH
= –12mA (2305- 1H)
REF = 0 MHz
Unloaded outputs, 66.66 MHz,
Te s t Conditions
—
—
M in.
—
2.0
—
—
—
2.4
—
—
M ax.
0.8
V
—
50.0
µA
200.0
0.4
V
—
50.0
50.0
µA
mA
Units
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2305-1
3.3V Zero-Delay Buffer
Operating Conditions
Parame te r
V
DD
T
A
(2305, 2305- 1H)
T
A
(2305I- 2305- 1HI)
C
L
C
IN
De s cription
Supply Voltage
Commercial Temperature (Ambient)
Industrial Temperature (Ambient)
Load Capacitance
Input Capacitance
M in.
3
0
–40
M ax.
3.6
70
ºC
85
30
pF
7
Units
V
Notes:
3. REF and CLK0 inputs have a threshhold voltage of V
DD
/2.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
PS9477A
06/06/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2305-1
3.3V Zero-Delay Buffer
Switching Characteristics
(4, 5)
(Over operating conditions)
Parame te rs
F
CLK
Name
Output Frequency
Duty Cycle
(4)
= t
2
÷ t
1
Duty Cycle
(4)
= t
2
÷ t
1
t
3
t
3
t
4
t
4
t
5
t
6
t
7
t
8
t
J
t
LOCK
Rise Time
(4)
@30pF
Rise Time
(4)
@30pF (H)
Fall Time
(4)
Te s t Conditions
30pF load
Measured at V
DD
/2,
F
OUT
< 66.66 MHz
Measured at 1.4V,
F
OUT
≤
45 MHz
M in.
10
45
40
Typ.
M ax.
100
Units
MHz
50
50
55
%
60
2.5
@ 30pF
Measured between
0.8V and 2.0V
1.5
ns
2.5
1.5
Fall Time
(4)
@30pF (H)
Output to Output Skew
(4)
Delay, REF Rising Edge to
CLK0 Rising Edge
(4)
Device to Device Skew
(4)
Output Slew Rate
(4)
Cycle to Cycle Jitter
(4)
PLL Lock Time
(4)
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the
output pins of devices
Measured between 0.8V and 2.0V
on - H device using Test Circuit #2
Measured at 66.67 MHz,
loaded outputs
Stable power supply, valid clocks
presented on REFpins
1
0
0
250
±350
700
V/ns
200
1. 0
ps
ms
ps
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. For definition of t
1-8
, see Switching Waveforms on page 5.
4
PS9477A
06/06/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2305-1
3.3V Zero-Delay Buffer
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
3.3V
2.0V
OUTPUT
0.8V
2.0V
0.8V
0V
t
3
,t
8
t
4
,t
8
Output-Output Skew
OUTPUT
1.4V
OUTPUT
1.4V
t
5
Input-Output Propagation Delay
INPUT
V
DD
/2
V
DD
/2
CLK[1:4]
t
6
Device-Device Skew
OUTPUT Device 1
V
DD
/2
OUTPUT Device 2
V
DD
/2
t
7
Test Circuit #1
V
DD
Test Circuit #2
0.1
0.1
µ
F
V
DD
µ
F
V
DD
1k
Ω
OUTPUTS
C
LOAD
V
DD
OUTPUTS
1k
Ω
10pF
0.1
µ
F
GND
GND
0.1
µ
F
GND
GND
T
est Circuit for all parameters except t
8
T
est Circuit for
t
8
,Output slew rate
on PI6C2305-1H device
5
PS9477A
06/06/00
Embedded System
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