8N3Q001EG-1142CDI datasheet, PDF

Datasheet> All Categories > Passive components> 8N3Q001EG-1142CDI

8N3Q001EG-1142CDI: DescriptionProgrammable Oscillators PROGRAMMABLE 5X7 OSCILLATOR; CategoryPassive components; File Size170KB，21 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet Parametric View All

8N3Q001EG-1142CDI Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	8N3Q001EG-1142CDI	-	-	View	Buy Now

8N3Q001EG-1142CDI Overview

Programmable Oscillators PROGRAMMABLE 5X7 OSCILLATOR

8N3Q001EG-1142CDI Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	IDT (Integrated Device Technology, Inc.)
Product Category	Programmable Oscillators
Product	XO
Package / Case	7 mm x 5 mm x 1.55 mm
Length	7 mm
Width	5 mm
Packaging	Bulk
Factory Pack Quantity	1
Unit Weight	0.006562 oz

Preview

Download Datasheet

View All

Quad-Frequency Programmable XO IDT8N3Q001 REV G

DATA SHEET

General Description

The IDT8N3Q001 is a Quad-Frequency Programmable Clock

Oscillator with very flexible frequency programming capabilities. The

device uses IDT’s fourth generation FemtoClock® NG technology for

an optimum of high clock frequency and low phase noise

performance. The device accepts 2.5V or 3.3V supply and is

packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x

7mm x 1.55mm package.

Besides the four default power-up frequencies set by the FSEL0 and

FSEL1 pins, the IDT8N3Q001 can be programmed via the I

interface to output clock frequencies between 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz to a very high degree of

precision with a frequency step size of 435.9Hz ÷

(N is the PLL

output divider). Since the FSEL0 and FSEL1 pins are mapped to 4

independent PLL M and N divider registers (P, MINT, MFRAC and N),

reprogramming those registers to other frequencies under control of

FSEL0 and FSEL1 is supported. The extended temperature range

supports wireless infrastructure, telecommunication and networking

end equipment requirements.

Features

•

Fourth generation FemtoClock® NG technology

Programmable clock output frequency from 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz

Four power-up default frequencies (see part number order

codes), re-programmable by I

C programming interface for the output clock frequency and

internal PLL control registers

Frequency programming resolution is 435.9Hz ÷N

One 2.5V, 3.3V LVPECL clock output

Two control inputs for the power-up default frequency

LVCMOS/LVTTL compatible control inputs

RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.244ps

(typical), integer PLL feedback configuration

RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.265ps

(typical), integer PLL feedback configuration

Full 2.5V or 3.3V supply modes

-40°C to 85°C ambient operating temperature

Available in Lead-free (RoHS 6) package

Block Diagram

OSC

XTAL

÷MINT,

MFRAC

FSEL1

FSEL0

SCLK

SDATA

Pulldown

Pullup

Pin Assignment

÷P

PFD

LPF

FemtoClock® NG

VCO

1950-2600MHz

÷N

Q

DNU 1

OE 2

FSEL0 4

FSEL1 5

10 SCLK

9 SDATA

8 V

7 nQ

6 Q

Configuration Register (ROM)

(Frequency, APR, Polarity)

C Control

IDT8N3Q001

10-lead Ceramic 5mm x 7mm x 1.55mm

package body

CD Package

Top View

IDT8N3Q001GCD REVISION A

MARCH 6, 2012

Recommended Resources

How to measure infrared photodiode sensitivity

Internal structure of remote operation inverter control circuit and remote operation panel

HT-821A0 circuit

TPS2014 typical application circuit diagram

KA2211 power amplifier circuit

Electronic gas igniter circuit

My first real work, although it only won the third prize: [b][b]It took about one and a half months to realize the functions of the analog intelligent highway street light control and monitoring system based on MSP430F149. Although I only won the third prize...; RCSN MCU

Pool resource release: 我在Filter种Attach的时候，分配了一个Pool: [code]NdisZeroMemory(&PoolParameters, sizeof(NET_BUFFER_LIST_POOL_PARAMETERS));PoolParameters.Header.Type = NDIS_OBJECT_TYPE_DEFAULT;PoolParameters.Header.Revision = NET_...; djzi_520 Embedded System

Strange problem with USB transmission: PC fails to read device data, but can write data! ! Please help!: I am currently working on the communication between USB host and device. The device chip is ARM7 and the PC is WinXp. I have encountered a problem: the host application can send data to the device (us...; bin8888 Embedded System

【CN0281】Single edge half byte (SENT) interface with cold junction compensation thermocouple automatic temperature sensor: ...; EEWORLD社区 ADI Reference Circuit

How to modify 256M RAM on 6410: 0x80000000, 0x50000000, 128 ; 128 MB DRAM DCD 0x80000000, 0x50000000, 256 ; 128 MB DRAM 3 Mempara_ddr.inc ; DMC1_MEM_CFG EQU ((1<<30)+(0<<21)+(0<<18)+(2<<15)+(0<<14)+(0<<13)+(0<<7)+(0<<6)+(2<<3)+(2<<0...; DSZ Embedded System

EEWORLD University ---- 2021_Digikey KOL Series: Application of New Intelligent Exposure Algorithm in Face Recognition: This year, DIGIKEY once again teamed up with well-known moderators to bring us the latest technical videos. This series of videos will be released in two parts. I hope that interested netizens will pa...; hi5 Training Edition

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components