IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
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DESCRIPTION
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The
ICSI
IC41C16257 and the IC41LV16257 are 262,144
Fast access and cycle time
x 16-bit high-performance CMOS Dynamic Random Access
TTL compatible inputs and outputs
Memory. Fast Page Mode allows 512 random accesses
Refresh Interval: 512 cycles/8 ms
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
Refresh Mode:
RAS-Only, CAS-before-RAS
byte, makes these devices ideal for use in 16-, 32-bit wide
(CBR), Hidden
data bus systems.
Self Refresh Mode: 512 cycles/64 ms (S version
These features make the IC41C16257 and the IC41LV16257
only)
ideally suited for high band-width graphics, digital signal
JEDEC standard pinout
processing, high-performance computing systems, and
peripheral applications.
Single power supply:
— 5V ± 10% (IC41C16257)
The IC41C16257 and the IC41LV16257 are packaged in a
40-pin, 400mil SOJ and TSOP-2.
— 3.3V ± 10% (IC41LV16257)
Byte Write and Byte Read operation via
KEY TIMING PARAMETERS
two
CAS
Parameter
-35
-50
-60 Unit
Available in 40-pin SOJ and TSOP-2
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
35
10
18
12
60
50
14
25
20
90
60
15
30
25
110
ns
ns
ns
ns
ns
PIN CONFIGURATIONS
40-Pin TSOP-2
40-Pin SOJ
Min. Read/Write Cycle Time (t
RC
)
PIN DESCRIPTIONS
A0-A8
I/O0-I/O15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address
Strobe
Lower Column Address
Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
FUNCTIONAL DESCRIPTION
The IC41C16257 and the IC41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by the
Row Address Strobe (RAS). The column address is latched
by the Column Address Strobe (CAS).
RAS
is used to latch
the first nine bits and
CAS
is used to latch the latter nine bits.
The IC41C16257 and the IC41LV16257 have two
CAS
controls,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs
internally generate a
CAS
signal functioning in an identical
manner to the single
CAS
input on the other 256K x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS). LCAS
controls
I/O0 - I/O7 and
UCAS
controls I/O8 - I/O15.
The IC41C16257/IC41LV16257
CAS
function is determined
by the first
CAS
(LCAS or
UCAS)
transitioning LOW and the
last transitioning back HIGH. The two
CAS
controls give the
IC41C16257 both BYTE READ and BYTE WRITE cycle
capabilities.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the ad-
dressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS
LOW. In
CAS-before-RAS
refresh cycle, an
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle must
not be initiated until the minimum precharge time t
RP
, t
CP
has
elapsed.
Self Refresh Cycle
(1)
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 64 ms. i.e.,
125 µs per row when using distributed CBR refreshes. The
feature also allows the user the choice of a fully static, low
power data retention mode. The optional Self Refresh feature
is initiated by performing a CBR Refresh cycle and holding
RAS
LOW for the specified t
RASS
.
The Self Refresh mode is terminated by driving
RAS
HIGH for
a minimum time of t
RPS
. This delay allows for the completion
of any internal refresh cycles that may be in process at the
time of the
RAS
LOW-to-HIGH transition. If the DRAM
controller uses a distributed refresh sequence, a burst refresh
is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a
RAS-only
or burst
refresh sequence, all 512 rows must be refreshed within the
average internal refresh rate, prior to the resumption of normal
operation.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are
all satisfied. As a result, the access time is dependent on the
timing relationships between these parameters.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with V
CC
or be held at a valid V
IH
to avoid current surges.
Note:
1.Self Refresh is for Sversion only.
Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
5
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