ANALOG DEVICES fAX-ON-DEHAND HOTLINE
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Page
23
W
I
ANALOG
DEVICES
FUNCTIONAL
12-Bit,100MSPS
UtAConverters
AD97121AD9713
I
FEATURES
100 MSPS Update Rate
ECL/TTL Compatibility
Low Glitch Impulse: 100 pV-s
Fast Settling: 30 ns to %1 LSB
Low Power: 700 mW
APPUCA TlONS
ATE
Signal
Reconstruction
Arbitrary Waveform Generators
Digital Synthesizers
Signal Generators
BLOCK DIAGRAM
AD9712/AD9713
OBS
rn
;1"
CONTROL
.!!.I CONTROL
m
ANALOG RETURN
113
GENERAL DESCRIPTION
The AD9712 and AD9713 are I2-bit, high speed digital-
to-analog converters constructed in an advanced oxide isolated
bipolar process. The AD9712 is an ECL-compatible device
featUring update rates of 100 MSPS minimum; the TTL-
compatible AD9713 will update at 80 MSPS minimum.
Designed for direct digital synthesis, waveform reconstruction,
and high resolution imaging applications, both devices feature
low glitch impulse of 100 pV-s; and fast settling times of 30 ns
to :!:1 LSB. Both units are characterized for dynamic perfor-
mance, and have excellent harmonic suppression.
OLE
TE
~2o)oo
REFERENCEY
OUT
L
o(191
YcONTROL
I AMP IN
c
0
The AD9712 and AD9713 are available in 28-pin plastic DIPs
and PLCCs, with an operating temperature range of 0 to + 70°C.
Contact the factory for availability of military-grade devices.
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iii
Q'
a
Q' Q
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5
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C
;i
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61 LATCH ENABLE
!I DIGITAL+V.
REFERENCE GROUND
221 REFERENCE
GROUND
~
:2J REFERENCE
OUT
AMP IN
AMP OUT
IN
REFERENCE OUT
AMP IN
191 CONTROL
REFERENCE
,:'
,
51 ANALOG-V.
9
:!
..
'"
I
-
,.,
Bwo
~
5
a.
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~ c:
II!
0
%::E
0
0
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Plastic DIPPinout Designations (Top View)
PLCC Pinout Designations
REV.A
Information furnished by Analog Devices is believed to be accurate and
reliable. However. no responsibility is assumed by Analog Devices for its
use. nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under
any
patent or patent rights of Analog Devices.
One Technology Way. P.O. Box 9106. Norwood. MA 02062-9106
Tel: 617/329-4700
Fax: 617/326-8703
Twx: 710/394-6577
We5t CQut
Central
Atlantic:
714/641-9391
214/231-5094
215/643.7790
RNRLOGDEVICES fRX-ON-DEnRND HOTLINE
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Page
2~
AD9712/AD9713
-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS!
Positive Supply Voltage (+Vs)(AD9713 Only) . . . . . . . .+6 V
Negative Supply Voltage (-Vs)
(AD9712andAD9713)
7V
DAC Outputs to ANALOG RETURN
. . . . . .+0.5
to -2 V
V
Digital Input Voltages (D1-D12' LATCH ENABLE)
AD9712
0Vto-Vs
AD9713
0Vto+Vs
Internal Reference Output Current. . . . . - 20 JLAto + 500 fLA
Control Amplifier Input Voltage Range
. . . . . . . .0V
to
-4 V
ControlAmplifierOutputCurrent
.:!:2.5mA
REFERENCE IN Voltage Range. . . . . . . . . .-3.7 V to -Vs
Analog Output Current (lOUT or lOUT)
.30 mA
Operating TemperatUre Range
AD9712]NIJP
Oto+70DC
AD9713]N/]P
Oto+70DC
Maximum Junction Temperature2
. . . . . . . . . . . . . . .+
IS0.C
Lead TemperatUre (Soldering, 10 seconds) . . . . . . . . .+ 300DC
Storage TemperatUre Range
.-65°C to + IS0DC
ELECTRICALCHARACTERISTICS
(-Vs
=
-5.2
V;+vs
OBS
Parameter (Conditions)
RESOLUTION
Temp
DC ACCURACY
Differential Nonlinearity Q)
Integral Nonlinearity Q)
«<Best Fit" Straight Line)
INITIAL OFFSET ERROR
Zero-SC4Ue ffset Error
O
Full-Scale Gain Error3
Offset Drift Coefficient
REFERENCE/CONTROL AMP
Internal Reference Voltage
Internal Reference Voltage Drift
Amplifier Input Impedance
Amplifier Bandwidth
REFERENCE INPtYf4
Reference Input Impedance
Reference Multiplying Bandwidths
OtITPUT PERFORMANCE
Full-Scale Output Currenr6
Output Compliance Range
Output Resistance
Output Capacitance
Output Update Rate7
Output Settling Time (tST)S
Current Settling
Voltage Settling (RL
=
50 fi)
Output Propagation Delay (tpD)9
Glitch Impulse1O
Output Slew Ratell
Output Rise Timeu
Output Fall Timell
+ 25"C
Full
+ 25"C
Full
I
VI
I
VI
+25°C
Full
+2sDC
Full
+25OC
I
VI
I
VI
V
+25OC
Full
Full
+25°C
+2SoC
+25°C
+2SoC
+ 25°C
+ 25OC
+25°C
+2sDC
+25DC
+2SoC
+2SoC
+2SoC
+2SoC
+2SoC
+2SOC
+25OC
I
I
V
V
V
V
V
V
IV
IV
V
IV
V
V
V
V
V
V
V
(external);
R$ET
=
1.5 kG,
unlessotherwisenoted)
Max
AD9713JNIJP
MiD
Typ
12
1.2
=
+5 V
(AD9713 Only); CONTROL
AMP
IN
=
-1.2 V
Units
Bits
LSB
LSB
LSB
LSB
Test
AD9112JN/JP
Level
MiD
Typ
12
1.2
Max
OLE
TE
2.0
4.0
3.0
4.0
2.0
4.0
3.0
4.0
0.5
4.0
1.5
5.0
8.5
11.0
0.5
1.5
5.0
4.0
8.5
11.0
0.03
0.03
IJoA
IJoA
%
%
p.ArC
-1.13
-1.11
- 1.26
- 1.39
-1.41
-1.13
-1.11
-1.26
- 1.39
V
-1.41
300
50
300
300
50
300
V
IJoV/oc
kO
kHz
3
40
20.48
-1.2
2.0
100
2.5
30
110
30
30
8
100
400
3
2
+3
3.0
-1.2
2.0
80
3
40
20.48
2.5
30
90
30
30
11
100
400
3
2
+3
3.0
kf!
MHz
mA
V
kf!
pF
M,SPS
ns
ns
ns
pV-s
V/s
ns
ns
-2-
REV.A
RNRLOGDEVICES fRK-ON-DEHRND HOTLINE
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Page
25
AD9712/AD9713
Parameter (Conditio
us)
DIGITAL INPUTS
Logic "I" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitallce
Input SetUp Time (t8)12
Input Hold Time (tiVU
Latch Pulse Width (tLPW)
(Transparent)
AC LINEARITY1.
Spurious-Free Dynamic Range
POWER SUPPL ylS
Positive Supply Current (+5.0
V)
Negative Supply Current (-5.2 V)
Temp
Full
Full
Full
Full
+ 25°C
+ 25°C
+ 25"C
+25"C
+25°C
+2S"C
Test
Level
VI
VI
VI
VI
V
V
V
V
V
I
VI
I
VI
V
I
AD97UJNIjP
MiD
Typ
Max
AD9713JNIjP
MiD
Typ
2.0
Mu.
Units
V
V
f.LA
pF
fiS
fiS
ns
dBc
-1.0
-0.8
-1.7
3
3
3
2.5
-60
-1.5
20
10
3
3
3
4
-55
10
0.8
20
600
OBS
Nominal Power Dissipation
Power Supply
Rejection Ratio (PSRR)16
+25°C
NOTES
14Update
rate s50
It
:t5%
Full
+ 25"C
Full
+25"C
130
676
50
160
170
350
135
726
50
20
23
165
175
350
mA
mA
mA
mA
mW
IJ.AN
'AbsolUte maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired.
Functioual operability is DOtnco:ssarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2"fypicaI thcrmal impedances: 28-pin plastic DIP 8J/\ = 4row;
8JC = 7"CIW; 28-pin PLCC 9,/\ = 48°C/Wj 8Jc = IOOCJW.
3Measured as error of me ratio of full-scale current to current throush RSET (160 IJ.Anominal); ratio is nominally 128.
4Pu11-scale variattous &moor devices are more severe when driving REFERENCE IN directly.
'Frequ~
at which a 3 dB reduction in output of DAC is observed; RL = 50 OJ 50% modulation at midscale.
when using internal amplifier.
6Based on Ips
=
128 (V~)
70utpUt settJin& to 0.1%.
'Measured at midscale transition, (0 :to.O24%.
'Measured from falling edge of LATCH ENABLE signal to 50% point of full.scale transition.
"'Glitch impuJlie combines me absolute value of positive and negarive transitions operating in latched mode.
uMcasurcd wim RL =
SO
0 and DAC operating in latched mode.
"Data must remain stable prior (0 falling edge of LATCH ENABLE signal for specified time.
13Data must remain stable after rising edge of LATCH ENABLE signal for specified time.
MSPS;
of
output
frequency
only)
=
5 MHz.
and
"Supply
16Mcasured
voltages should remain stable within :t5% for normal operation.
+ V s (AD9713
-
V s (AD9712
OLE
TE
or AD9713)
using
external
reference.
Specifications subject to chance withoUt ponce.
EXPLANATION
Level
I
OF TEST LEVELS
Model
ORDERING GUIDE
Package
Option.
N-28
P-28A
N-28
P-28A
-
II
-
100% production
tested.
Description
ECL-Compatible Plastic DIP
ECL-Compatible PLCC
ITL-Compatible Plastic DIP
ITL-Compatib1e PLCC
DIP; P
100% production tested at + 25°C. and sample tested at
specifiedtemperatures.
III - Sampletested only.
IV - Parameteris guaranteedby design and
characterizationtesting.
V
-
Parameter is a typical value only.
VI
AD9712JN
AD9712JP
AD97I3JN
AD9713JP
*N
=
Plastic
=
Plastic
Leaded Chip Carrier.
-
All devices arc 100% production tested at +25°C. 100%
production tested at temperatUre extremes for extended
temperature devices; sample tested at temperature
exttcmes for commercial/industrial devices.
REV. A
-3-
ANALOGDEVICES fAX-ON-DEMAND HOTLINE
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AD9713/AD9713
AD911Z1AD9713 DESCRIPTIONS
PIN
Pia
Fanctioll
No.
Name
1-10
11
12
13
D2-D11
D12 (LSB)
DIGITAL -Vs
ANALOG RETURN
Ten of twelve digital input bits.
Least Significant Bit (LSB) of digital input word.
One of two negative digital supply pins; nominally -5.2 V.
Analog ground retUrn. This point and the reference side of the
DAC load resistors should be connected to the same potential
(nominally ground).
Analog current output; full-scale output occurs with digital
inputs at all "I."
One of two negative analog supply pins; nominally -5.2 V.
Complementary analog current output; zero scale output occurs
with digital inputs at all "1."
Normally connected to CONTROL AMP OUT (Pin 18). Direct
line to DAC current switch network. Voltage changes at this
point have a direct effect on the full-scale output. Full-scale
current output"" 128 (Reference voltageIRsET) when using
internal amplifier.
Normallyoonnected to REFERENCE IN (pin 17). Output of
internal control amplifier, which provides a temperature
oompensated drive level to the current switch network.
connected
to external reference.
Full-scale current
out
14
15
16
17
loUT
ANALOG -Vs
loUT
REFERENCE IN
OBS
18
CONTROL AMP OUT
19
CONTROL AMP IN
20
21
22
23
24
REFERENCE OUT
DIGITAL -Vs
REFERENCE GROUND
DIGITAL +Vs
RsET
Normally connected to REFERENCE OUT (pin 20) if not
(Reference voltageIRsET) when using internal amplifier.
Normally connected to CONTROL AMP IN (pin 19). Internal
voltage reference, nominally -1.26 V.
One of two negative digital supply pins; nominally
Ground return for the internal voltage reference and amplifier.
Positive digital supply pin; used only on the AD9713; nominally
+5V.
Connection for external resistance reference. Full-scale current
out
128 (Reference voltagelRsET) when using internal
amplifier.
OLE
TE
=
128
- 5.2 V.
=
25
26
27
28
ANALOG -Vs
LATCH ENABLE
DIGITAL GROUND
D1 (MSB)
One of two negative analog supply pins; nominally -5.2 V.
Transparent latch coDtrolline.
Digital ground retUrn.
Most Significant Bit (MSB) of digital input word.
LATCH
ENABLE
LATCH ENABLE
OUTPUT
ERROR
DATA HOUrS
OUTPUT
./
t..-
-
t
..
I
ST
t
I'D
t.
-
-
LATCHPULSEWIOTIf
INPUTSETUPTIIE
INPUT HOLD TIME
OUT'POT SETTUHO TIME
OUT'POT
PROPAGA11ON
DELAY
-
-
AD97121AD9713 Timing Diagram
-4-
REV.
A
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RNRLOGDEVICES fRX-ON-DEHRND HOTLINE
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27
AD9712/AD9713
THEORY AND APPUCATIONS
The AD9712 and AD9713 high speed digital-to-analog conven-
ers utilize Most Significant Bit (MSB) decoding and segmenta-
tion techniques to reduce glitch impulse and maintain linearity
without trimming.
As shown in the functional block diagram, the design is based
on four main subsections: the DecoderlDriver circuits, the
Transparent Latches, the Switch Network and the Control
Amplifier. An internal band-gap reference is also included to
allow operation with a minimum of external components.
Digital Inputs
The AD9712 employs single-cnded ECL-compatible inputs for
data inpUtS DI-D12 and LATCH ENABLE. The internal ECL
midpoint reference is designed to match 10K ECL device
thresholds. On the AD9713, a TTL translator is added at
each input; with this exception, the AD9712 and AD9713 are
identical.
greater accuracy or better temperature stability is required, an
external reference can be utilized. The AD589 reference shown
in Figure I features :t 10 ppm?C drift over temperatUres from 0
to +70°C.
A09712
A09713
:II1)CON'TROl
4MP IN
R,
::11kl)
-VI
Figure
1.
Use of A 0589
8S
External Reference
Two modes of multiplying operation are possibl~ with the
AD97121AD9713. Signals with bandwidths up to 400 kHz and
input swings from -0.1 V to -1.2 V can be applied to the
CONTROL AMP input as shown in Figure 2. Because the con-
trol amplifier is internally compensated, the 0.1 J.LFcapacitor at
Pin 17 can be eliminated to maximize the multiplying band-
width. However, it should be noted that settling time for
changes to the digital inputs will be degraded.
OBS
In the DecoderlDriver section, the four MSBs (DcDJ are
decoded to 15 "thermometer code" lines. An equalizing delay is
included for the eight Least Significant Bits (LSBs) and
LATCH ENABLE. This delay minimizes data skew, and data
setup and hold times at the latch inputs; this is important when
operating the latches in the transparent mode. Without the
delay, skew caused by the decoding circuits would degrade
glitch impulse.
The latches operate in their transparent mode when LATCH
ENABLE (Pin 26) is at logic level "0." The latches can be used
to synchronize data to the current switches by applying a narrow
LATCH ENABLE pulse with proper data setup and hold times
as shown in the timing diagram. With an external transparent
latch at each data input clocked out of phase with the DAC, the
AD97121AD9713 operates in a master slave (edge-triggered)
mode.
Although the AD97121AD9713 chip is designed to provide isola-
tion from digital inputs to the outputs, some coupling of digital
transitions is inevitable, especially with TTL or CMOS inputs
applied to the AD9713. Digital feedthrough can be reduced by
forming a low-pass filter using a resistor in series with the
capacitance of each digital input.
References
As shown in the functional block diagram, the internal band-gap
reference, control amplifier and reference input are pinned out
for maximum user flexibility when setting the reference.
OLE
TE
.IJ.6Vlo.l.2V
181l
Figure
2.
Low Frequency Multiplying Circuit
The REFERENCE IN pin can also be driven directly
for
wider
bandwidth multiplying operation. The analog signal
for
this
mode of operation must have a signal swing in the range of
-4 V to -5.2 V. This can be implemented by capacitively cou-
pling into REFERENCE IN an ac signal and establishing a de
bias of -4.0 V to -5.2 V, as shown in Figure 3; or by driving
REFERENCE IN with a low impedance op amp whose signal
swing is limited to the stated range.
AD9712
AD9713
4k1l
When using the internal reference, REFERENCE OUT (Pin 20)
should be connected to CONTROL AMP IN (pin 19). CON-
TROL AMP OUT (pin 18) should be connected to REFER-
ENCE IN (Pin 17) through an 18 n resistor. A 0.1 J.LF
ceramic
capacitor from Pin 17 to -Vs (pin 15) improves settling by
decoupllng switching noise
from
the current sink base line. A
reference current cell provides feedback to the control amp by
sinking current through Rsn (Pin 24).
Full-scale output current is determined by the voltage at CON-
TROL AMP IN (VREF)and Rsn according to the
equation:
lOUT
IPS)
ANAl~
>
O.I~FI
1.2k11
=
VREFIRsET
x 128.
-V.
-vo
The internal reference is nominally
-
1.26 V with a tolerance of
:t 10% and typical drift over temperature of 300 J.Lrc. If
v
Figure
3.
Wideband Multiplying
Circuit
-5-
REV. A
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