AV9172-07 datasheet, PDF - EEWORLD Datasheet

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AV9172-07: DescriptionLow Skew Output Buffer; File Size287KB，8 Pages; ManufacturerICS ( IDT ); Websitehttp://www.icst.com

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AV9172-07 Overview

Low Skew Output Buffer

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Integrated

Circuit

Systems, Inc.

AV9172

Low Skew Output Buffer

General Description

The

AV9172

is designed to generate low skew clocks for

clock distribution in high-performance PCs and workstations.

It uses phase-locked loop technology to align the phase and

frequency of the output clocks with an input reference clock.

Because the input to output skew is guaranteed to ±500ps, the

part acts as a “zero delay” buffer.

The

AV9172

has six configurable outputs. The

AV9172-01

version has one output that runs at the same phase and

frequency as the reference clock. A second output runs at the

same frequency as the reference, but can either be in phase or

180° out of phase from the input clock. Two outputs are

provided that are at twice the reference frequency and in

phase with the reference clock. The final outputs can be

programmed to be replicas of the 2x clocks or non-overlapping

two phase clocks at twice the reference frequency. The

AV9172-01

and

AV9172-03

operates with input clocks

from 10 MHz to 50 MHz while producing outputs from

10 MHz to 100 MHz. The

AV9172-07

operates with input

clocks from 20 to 100 MHz.

The use of a phase-locked loop (PLL) allows the output

clocks to run at multiples of the input clock. This permits

routing of a lower speed clock and local generation of a

required high speed clock. Synchronization of the phase

relationship between the input clock and the output clocks is

accomplished when one output clock is connected to the

input pin FBIN. The PLL circuitry matches rising edges of the

input clock and output clocks.

Features

AV9172-07

input is 66 MHz with 66 and 33 MHz

output buffers

• AV9172-01

is pin compatible with Gazelle GA1210E

• ±250ps skew (max) between outputs

• ±500ps skew (max) between input and outputs

• Input frequency range from 10 MHz to 50 MHz

(-01, -03) and from 20 MHz to 100 MHz (-07)

• Output frequency range from 10 MHz to 100 MHz

(-01, -03, -07)

• Special mode for two-phase clock generation

• Inputs and outputs are fully TTL-compatible

• CMOS process results in low power supply current

• High drive, 25mA outputs

• Low cost

• 16-pin SOIC (150-mil) or 16-pin PDIP package

The

AV9172

is fabricated using CMOS technology which

results in much lower power consumption and cost compared

with the gallium arsenide-based GA1210E. The typical

operating current for the

AV9172

is 50mA versus 120mA for

the GA1210E.

ICS offers several versions of the

AV9172.

The different

devices are shown below:

PART

AV9172-01

AV9172-03

AV9172-07

DESCRIPTION

Second source of GA1210E

Clock doubler and buffer

Clock buffer for 66 MHz input

•

Block Diagram

AV9172RevB060297P

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.

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