73S1210F
Self-Contained Smart Card Reader
with PINpad and Power Management
Simplifying System Integration™
DATA SHEET
May 2009
GENERAL DESCRIPTION
The 73S1210F is a versatile and economical CMOS
System-on-Chip device intended for smart card reader
applications. The circuit is built around an 80515 high-
performance core; it features primarily an ISO-7816 / EMV
interface and a generic asynchronous serial interface.
Delivered with turnkey Teridian embedded firmware, it
forms a ready-to-use smart card reader solution that can be
seamlessly incorporated into any microprocessor-based
system where a serial line is available.
The solution is scalable, thanks to a built-in I
2
C interface
that allows to drive external electrical smart card interfaces
such as Teridian 73S8010 ICs. This makes the solution
immediately able to support multi-card slots or multi-SAM
architectures.
In addition, the 73S1210 features a 5x6 PINpad interface, 8
user I/Os, multiple interrupt options and an analog voltage
input (for DC voltage monitoring such as battery level
detection) that make it suitable for low-cost PINpad reader
devices.
The 80515 CPU core instruction set is compatible with the
industry standard 8051, while offering one clock-cycle per
instruction processing power (most instructions). With a
CPU clock running up to 24MHz, it results in up to 24MIPS
available that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance).
The circuit requires a single 6MHz to 12MHz crystal.
The respective 73S1210F embedded memories are 32KB
Flash program memory, 2KB user XRAM memory, and
256B IRAM memory. Dedicated FIFOs for the ISO 7816
UART are independent from the user XRAM and IRAM.
Alternatively to the turnkey firmware offered by Teridian,
customers can develop their own embedded firmware
directly within their application or using Teridian 73S1210F
Evaluation Board through a JTAG-like interface.
The chip incorporates an inductor-based DC-DC converter
that generates all the necessary voltages to the various
73S1210F function blocks (smart card interface, digital
core, etc.) from any of two distinct power supply sources:
the +5V bus (V
BUS
, 4.4 to 6.5V), or a main battery (V
BAT
,
4.0V to 6.5V). The chip automatically powers-up the DC-
DC converter with V
BUS
if it is present, or uses V
BAT
as the
supply input if V
BUS
is not present. Alternatively, the pin V
PC
can support a wider power supply input range (2.7V to
6.5V), when using a single system supply source.
In addition, the circuit features an ON/OFF mode which
operates directly with an ON/OFF system switch: Any
activity on the ON/OFF button is debounced internally
and controls the power generation circuit accordingly,
under the supervision of the firmware (OFF request /
OFF acknowledgement at firmware level). The OFF
mode can be alternatively initiated from the controller
(firmware action instead of ON/OFF switch).
In OFF mode, the circuit typically draws less than 1µA,
which makes it ideal for applications where battery life
must be maximized.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the 73S1210F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1210F a very comprehensive set of software
libraries for EMV. Refer to the
73S12xxF Software
User’s Guide
for a complete description of the
Application Programming Interface (API Libraries) and
related software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable rapid
development and certification of readers that meet
most demanding smart card standards.
APPLICATIONS
•
PINpad smart card readers:
o
With serial connectivity
o
Ideal for low-cost POS Terminals and Digital
Identification (Secure Login, Gov’t ID, ...)
SIM Readers in Personal Wireless devices
Payphones & Vending machines
General purpose smart card readers
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ADVANTAGES
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Reduced BOM
Versatile power supply options
o
2.7V to 6.5V ranges
Higher performance CPU core (up to 24MIPS)
Built-in EMV/ISO slot, expandable to multi-slots
Flexible power supply options
o
On-chip DC-DC converter
o
CMOS switches between supply inputs
Sub-µA Power Down mode with ON/OFF switch
Powerful In-Circuit Emulation and Programming
A complete set of EMV4.1 / ISO7816 libraries
Turnkey PC/SC firmware and host drivers
o
Multiple OS supported
Rev. 1.4
© 2009 Teridian Semiconductor Corporation
1
73S1210F Data Sheet
FEATURES
80515 Core:
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1 clock cycle per instruction (most instructions)
CPU clocked up to 24MHz
32KB Flash memory (lockable)
2kB XRAM (User Data Memory)
256 byte IRAM
Hardware watchdog timer
Single low-cost 6MHz to 12MHz crystal
An Internal PLL provides all the necessary clocks to
each block of the system
Standard 80C515 4-priority level structure
9 different sources of interrupt to the core
2 standard 80C515 Power Down and IDLE modes
Sub-µA OFF mode
ON/OFF Main System Power Switch:
Input for an SPST momentary switch to ground
(2) Standard 80C52 timers T0 and T1
(1) 16-bit timer
Linear regulator produces VCC for the card
(1.8V, 3V or 5V)
Full compliance with EMV 4.1
Activation/Deactivation sequencers
Auxiliary I/O lines (C4 and C8 signals)
7kV ESD protection on all interface pins
ISO 7816 UART 9600 to 115kbps for T=0, T=1
(2) 2-Byte FIFOs for transmit and receive
Configured to drive multiple external Teridian
73S8010x interfaces (for multi-SAM architectures)
Analog Input (detection range: 1.0V to 2.5V)
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DS_1210F_001
Communication Interfaces:
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Full-duplex serial interface (1200 to 115kbps
UART)
I
2
C Master Interface (400kbps)
Man-Machine Interface and I/Os:
6x5 Keyboard (hardware scanning, debouncing
and scrambling)
(8) User I/Os
Single programmable current output (LED)
Operating Voltage:
Single supply 2.7V to 6.5V operation (VPC)
5V supply (VBUS 4.4V to 5.5V) with or without
battery back up operation (VBAT 4.0V to 6.5V)
Automated detection of voltage presence - Priority
on VBUS over VBAT
Requires a single 10µH Inductor
3.3V / 20mA supply available for external circuits
-40°C to 85°C
68-pin QFN, 44 pin QFN
Compliant with PC/SC, ISO7816 and EMV4.1
specifications
Features a Power Down mode accessible from the
host
Supports Plug & Play over serial interface
®
Windows XP driver available (*)
Oscillators:
Interrupts:
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Power Down Modes:
DC-DC Converter:
Operating Temperature:
Package:
Turnkey Firmware:
Timers:
Built-in ISO-7816 Card Interface:
Windows CE / Mobile driver available (*)
Linux and other OS: Upon request
Or for custom developments:
o
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A complete set of ISO-7816, EMV4.1 and
low-level libraries are available for T=0 / T=1
Two-level Application Programming Interface
(ANSI C-language libraries)
Communication with Smart Cards:
Voltage Detection:
•
(*) Contact Teridian Semiconductor for conditions and
availability.
2
Rev. 1.4
DS_1210F_001
73S1210F Data Sheet
Table of Contents
1
Hardware Description ......................................................................................................................... 8
1.1 Pin Description ............................................................................................................................. 8
1.2 Hardware Overview ................................................................................................................... 11
1.3 80515 MPU Core ....................................................................................................................... 11
1.3.1 80515 Overview ............................................................................................................. 11
1.3.2 Memory Organization .................................................................................................... 11
1.4 Program Security ....................................................................................................................... 16
1.5 Special Function Registers (SFRs) ........................................................................................... 18
1.5.1 Internal Data Special Function Registers (SFRs).......................................................... 18
1.5.2 IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19
1.5.3 External Data Special Function Registers (SFRs) ........................................................ 20
1.6 Instruction Set ............................................................................................................................ 22
1.7 Peripheral Descriptions .............................................................................................................. 22
1.7.1 Oscillator and Clock Generation .................................................................................... 22
1.7.2 Power Supply Management .......................................................................................... 25
1.7.3 Power ON/OFF .............................................................................................................. 26
1.7.4 Power Control Modes .................................................................................................... 27
1.7.5 Interrupts ........................................................................................................................ 33
1.7.6 UART ............................................................................................................................. 40
1.7.7 Timers and Counters ..................................................................................................... 45
1.7.8 WD Timer (Software Watchdog Timer) ......................................................................... 47
1.7.9 User (USR) Ports ........................................................................................................... 49
1.7.10 Analog Voltage Comparator .......................................................................................... 51
1.7.11 LED Driver ..................................................................................................................... 53
1.7.12 I
2
C Master Interface ....................................................................................................... 54
1.7.13 Keypad Interface ............................................................................................................ 61
1.7.14 Emulator Port ................................................................................................................. 68
1.7.15 Smart Card Interface Function ...................................................................................... 69
1.7.16 VDD Fault Detect Function .......................................................................................... 103
Typical Application Schematic ...................................................................................................... 104
Electrical Specification................................................................................................................... 105
3.1 Absolute Maximum Ratings ..................................................................................................... 105
3.2 Recommended Operating Conditions ..................................................................................... 105
3.3 Digital IO Characteristics ......................................................................................................... 106
3.4 Oscillator Interface Requirements ........................................................................................... 107
3.5 DC Characteristics: Analog Input............................................................................................. 107
3.6 Smart Card Interface Requirements ........................................................................................ 108
3.7 DC Characteristics ................................................................................................................... 110
3.8 Current Fault Detection Circuits............................................................................................... 111
Equivalent Circuits ......................................................................................................................... 112
Package Pin Designation ............................................................................................................... 120
5.1 68-pin QFN Pinout ................................................................................................................... 120
5.2 44-pin QFN Pinout ................................................................................................................... 121
Packaging Information ................................................................................................................... 122
6.1 68-Pin QFN Package Outline .................................................................................................. 122
6.2 44-Pin QFN Package Outline .................................................................................................. 123
Ordering Information ...................................................................................................................... 124
Related Documentation .................................................................................................................. 124
Contact Information ........................................................................................................................ 124
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3
4
5
6
7
8
9
Revision History ...................................................................................................................................... 125
Rev. 1.4
3
73S1210F Data Sheet
DS_1210F_001
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 7
Figure 2: Memory Map ................................................................................................................................ 15
Figure 3: Clock Generation and Control Circuits ........................................................................................ 22
Figure 4: Oscillator Circuit ........................................................................................................................... 24
Figure 5: Detailed Power Management Logic Block Diagram .................................................................... 25
Figure 6: Power Down Control .................................................................................................................... 27
Figure 7: Detail of Power Down Interrupt Logic .......................................................................................... 28
Figure 8: Power Down Sequencing ............................................................................................................ 29
Figure 9: External Interrupt Configuration ................................................................................................... 33
Figure 10: I
2
C Write Mode Operation .......................................................................................................... 55
Figure 11: I
2
C Read Operation ................................................................................................................... 56
Figure 12: Simplified Keypad Block Diagram ............................................................................................. 61
Figure 13: Keypad Interface Flow Chart ..................................................................................................... 63
Figure 14: Smart Card Interface Block Diagram ......................................................................................... 69
Figure 15: External Smart Card Interface Block Diagram .......................................................................... 70
Figure 16: Asynchronous Activation Sequence Timing .............................................................................. 73
Figure 17: Deactivation Sequence .............................................................................................................. 73
Figure 18: Smart Card CLK and ETU Generation ...................................................................................... 74
Figure 19: Guard, Block, Wait and ATR Time Definitions .......................................................................... 75
Figure 20: Synchronous Activation ............................................................................................................. 77
Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 77
Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode ................................. 78
Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 78
Figure 24: Operation of 9-bit Mode in Sync Mode ...................................................................................... 79
Figure 25: 73S1210F Typical Application Schematic ............................................................................... 104
Figure 26: 12 MHz Oscillator Circuit ......................................................................................................... 112
Figure 27: 32KHz Oscillator Circuit ........................................................................................................... 112
Figure 28: Digital I/O Circuit ...................................................................................................................... 113
Figure 29: Digital Output Circuit ................................................................................................................ 113
Figure 30: Digital I/O with Pull Up Circuit .................................................................................................. 114
Figure 31: Digital I/O with Pull Down Circuit ............................................................................................. 114
Figure 32: Digital Input Circuit ................................................................................................................... 115
Figure 33: OFF_REQ Interface Circuit ..................................................................................................... 115
Figure 34: Keypad Row Circuit ................................................................................................................. 115
Figure 35: Keypad Column Circuit ............................................................................................................ 116
Figure 36: LED Circuit ............................................................................................................................... 116
Figure 37: Test and Security Pin Circuit ................................................................................................... 117
Figure 38: Analog Input Circuit ................................................................................................................. 117
Figure 39: Smart Card Output Circuit ....................................................................................................... 117
Figure 40: Smart Card I/O Circuit ............................................................................................................. 118
Figure 41: PRES Input Circuit ................................................................................................................... 118
Figure 42: PRESB Input Circuit ................................................................................................................ 118
Figure 43: ON_OFF Input Circuit .............................................................................................................. 119
Figure 44: 73S1210F 68 QFN Pinout ....................................................................................................... 120
Figure 45: 73S1210F 44 QFN Pinout ....................................................................................................... 121
Figure 46: 73S1210F 68 QFN Mechanical Drawing ................................................................................. 122
Figure 47: 73S1210F 44 QFN Package Drawing ..................................................................................... 123
4
Rev. 1.4
DS_1210F_001
73S1210F Data Sheet
Tables
Table 1: 73S1210 Pinout Description ........................................................................................................... 8
Table 2: MPU Data Memory Map ............................................................................................................... 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................ 18
Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register................................................................................................................................ 21
Table 10: Port Registers ............................................................................................................................. 21
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 23
Table 12: The MCLKCtl Register ................................................................................................................ 23
Table 13: The TCON Register .................................................................................................................... 24
Table 14: The INT5Ctl Register .................................................................................................................. 30
Table 15: The MISCtl0 Register.................................................................................................................. 30
Table 16: The MISCtl1 Register.................................................................................................................. 31
Table 17: The MCLKCtl Register ................................................................................................................ 31
Table 18: The PCON Register .................................................................................................................... 32
Table 19: The IEN0 Register ...................................................................................................................... 34
Table 20: The IEN1 Register ...................................................................................................................... 35
Table 21: The IEN2 Register ...................................................................................................................... 35
Table 22: The TCON Register .................................................................................................................... 36
Table 23: The T2CON Register .................................................................................................................. 36
Table 24: The IRCON Register ................................................................................................................... 37
Table 25: External MPU Interrupts.............................................................................................................. 37
Table 26: Control Bits for External Interrupts .............................................................................................. 38
Table 27: Priority Level Groups .................................................................................................................. 38
Table 28: The IP0 Register ......................................................................................................................... 38
Table 29: The IP1 Register ......................................................................................................................... 39
Table 30: Priority Levels.............................................................................................................................. 39
Table 31: Interrupt Polling Sequence.......................................................................................................... 39
Table 32: Interrupt Vectors ......................................................................................................................... 39
Table 33: UART Modes .............................................................................................................................. 40
Table 34: Baud Rate Generation ................................................................................................................ 40
Table 35: The PCON Register .................................................................................................................... 41
Table 36: The BRCON Register ................................................................................................................. 41
Table 37: The MISCtl0 Register.................................................................................................................. 42
Table 38: The S0CON Register .................................................................................................................. 43
Table 39: The S1CON Register .................................................................................................................. 44
Table 40: The TMOD Register .................................................................................................................... 45
Table 41: Timers/Counters Mode Description ............................................................................................ 45
Table 42: The TCON Register .................................................................................................................... 46
Table 43: The IEN0 Register ...................................................................................................................... 47
Table 44: The IEN1 Register ...................................................................................................................... 48
Table 45: The IP0 Register ......................................................................................................................... 48
Table 46: The WDTREL Register ............................................................................................................... 48
Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49
Table 48: UDIR Control Bit ......................................................................................................................... 49
Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 49
Table 50: The USRIntCtl1 Register ............................................................................................................ 50
Table 51: The USRIntCtl2 Register ............................................................................................................ 50
Table 52: The USRIntCtl3 Register ............................................................................................................ 50
Table 53: The USRIntCtl4 Register ............................................................................................................ 50
Table 54: The ACOMP Register ................................................................................................................. 51
Table 55: The INT6Ctl Register .................................................................................................................. 52
Table 56: The LEDCtl Register ................................................................................................................... 53
Rev. 1.4
5
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