Index
AN-937 (v.Int)
Gate Drive Characteristics and Requirements for
HEXFET
®
s
Topics covered:
Gate drive vs base drive
Enhancement vs Depletion
N vs P-Channel
Max gate voltage
Zener diodes on gate?
The most important factor in gate drive: the impedance of the gate drive circuit
Switching 101 or Understanding the waveforms
What happens if gate drive impedance is high? dv/dt induced turn-on
Can a TTL gate drive a standard HEXFET
®
?
The universal buffer
Power dissipation of the gate drive circuit is seldom a problem
Can a C-MOS gate drive a standard HEXFET
®
?
Driving HEXFET
®
s from linear circuits
Drive circuits not referenced to ground
Gate drivers with optocouplers
Gate drive supply developed from the drain of the power device
Gate drivers with pulse transformers
Gate drivers with choppers
Drive requirements of Logic Level HEXFET
®
s
How fast is a Logic Level HEXFET
®
driven by a logic circuit?
Simple and inexpensive isolated gate drive supplies
A well-kept secret: Photovoltaic generators as gate drivers
Driving in the MHz? Use resonant gate drivers
Related topics
(Note: Most of the gate drive considerations and circuits are equally applicable to IGBTs. Only MOSFETs are mentioned for the
sake of simplicity. Special considerations for IGBTs are contained in INT-990)
1. GATE DRIVE VS BASE DRIVE
The conventional bipolar
transistor is a current-driven
device. As illustrated in
Figure 1(a). a current must
be applied between the base
and emitter terminals to pro-
duce a flow of current in the
collector. The amount of a
drive required to produce a
given output depends upon
the gain, but invariably a
current must be made to flow
into the base terminal to
produce a flow of current in
the collector.
CURRENT
IN BASE
PRODUCES
CURRENT
IN COLLECTOR
I
C
I
B
VOLTAGE
AT GATE
+
+
+
PRODUCES
CURRENT
IN DRAIN
I
D
CURRENT
SOURCE
(a) Bipolar Transistor
VOLTAGE
SOURCE
(b) HEXFET
Figure 1.
Bipolar Transistor is Current Driven, HEXFET is Voltage Driven
The HEXFET
®
is fundamentally different: it is a voltage-controlled power MOSFET device. A voltage must be applied between
the gate and source terminals to produce a flow of current in the drain (see Figure 1b). The gate is isolated electrically from the
source by a layer of silicon dioxide. Theoretically, therefore, no current flows into the gate when a DC voltage is applied to it -
though in practice there will be an extremely small current, in the order of nanoamperes. With no voltage applied between the
gate and source electrodes, the impedance between the drain and source terminals is very high, and only the leakage current
flows in the drain.
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When a voltage is applied between the gate and
source terminals, an electric field is set up within the
HEXFET
®
. This field “inverts” the channel (Figure
2) from P to N, so that a current can flow from drain
to source in an uninterrupted sequence of N-type
silicon (drain-channel-source). Field-effect
transistors can be of two types: enhancement mode
and depletion mode. Enhancement-mode devices
need a gate voltage of the same sign as the drain
voltage in order to pass current.
Depletion-mode devices are naturally on and are
turned off by a gate voltage of the same polarity as
the drain voltage. All HEXFET
®
s are enhancement-
mode devices.
AN-937 (v.Int)
SOURCE
METALLIZATION
SILICON GATE
CHANNEL
INSULATING
OXIDE
P
N
SOURCE
GATE OXIDE
N
N
TRANSISTOR
TRANSISTOR
DRAIN
DRAIN
All MOSFET voltages are referenced to the source
CURRENT
CURRENT
terminal. An N-Channel device, like an NPN
transistor, has a drain voltage that is positive with
respect to the source. Being enhancement-mode
DIODE CURRENT
devices, they will be turned on by a positive voltage
Figure 2.
Basic HEXFET Structure
on the gate. The opposite is true for P-Channel
devices, that are similar to PNP transistors.
Although it is common knowledge that HEXFET
®
transistors are more easily driven than bipolars, a few basic considerations
have to be kept in mind in order to avoid a loss in performance or outright device failure.
2. GATE VOLTAGE LIMITATIONS
Figure 2 shows the basic HEXFET
®
structure. The silicon oxide layer between the gate and the source regions can be punctured
by exceeding its dielectric strength. The data sheet rating for the gate-to-source voltage is between 10 and 30 V for most
HEXFET
®
s.
Care should be exercised not to exceed the gate-to-source maximum voltage rating. Even if the applied gate voltage is kept below
the maximum rated gate voltage, the stray inductance of the gate connection, coupled with the gate capacitance, may generate
ringing voltages that could lead to the destruction of the oxide layer. Overvoltages can also be coupled through the drain-gate
self-capacitance due to transients in the drain circuit. A gate drive circuit with very low impedance insures that the gate voltage
is not exceeded in normal operation. This is explained in more detail in the next section.
Zeners are frequently used “to protect the gate from transients”. Unfortunately they also contribute to oscillations and have been
known to cause device failures. A transient can get to the gate from the drive side or from the drain side. In either case, it would
be an indication of a more fundamental problem: a high impedance drive circuit. A zener would compound this problem, rather
than solving it. Sometimes a zener is added to reduce the ringing generated by the leakage of a gate drive transformer, in
combination with the input capacitance of the MOSFET. If this is necessary, it is advisable to insert a small series resistor (5-10
Ohms) between the zener and the gate, to prevent oscillations.
3. THE IMPEDANCE OF THE GATE CIRCUIT
To turn on a power MOSFET a certain charge has to be supplied to the gate to raise it to the desired voltage, whether in the
linear region, or in the “saturation” (fully enhanced) region. The best way to achieve this is by means of a voltage source, capable
of supplying any amount of current in the shortest possible time. If the device is operated as a switch, a large transient current
capability of the drive circuit reduces the time spent in the linear region, thereby reducing the switching losses.
On the other hand, if the device is operated in the linear mode, a large current from the gate drive circuit minimizes the
relevance of the Miller effect, improving the bandwidth of the stage and reducing the harmonic distortion. This can be better
understood by analyzing the basic switching waveforms at turn-on and turn-off for a clamped inductive load, as shown in Figures
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Index
AN-937 (v.Int)
3 and 5. Figure 3 shows the waveforms of the drain current, drain-to-source voltage and gate voltage during the turn-on interval.
For the sake of simplicity, the equivalent impedance of the drive circuit has been assumed as purely resistive.
DRAIN-SOURCE
VOLTAGE
LOAD
DRAIN-SOURCE
I
STRAY
INDUCTANCE
DRIVE CIRCUIT
RESISTANCE
G
LSE
PU
E
RIV
"D
IT
CU
CIR
EN
"OP
V
TH
t
0
t
1
t
2
t
3
t
4
GATE-SOURCE
VOLTAGE
"OPEN CIRCUIT"
DRIVE
PULSE
SOURCE
INDUCTANCE
Figure 3.
Waveforms at Turn-On
VOLTAGE DROP ACROSS
THIS L MEANS THAT THE
DRAIN VOLTAGE FALL
RESULTING IN
DISCHARGE OF
THIS CAPACITOR
RESULTING IN
MORE CURRENT
THROUGH THIS
RESISTANCE
+
DRAIN-SOURCE
VOLTAGE
I
D
CURRENT
-
I
DRIVE
+
-
I
S
THIS INDUCED VOLTAGE
SUBSTRACTS FROM THE
DRIVE VOLTAGE
RESULTING IN
G-S VOLTAGE
"OPEN CIRCUIT"
DRIVE PULSE
t
0
t
1
t
2
t
4
GATE VOLTAGE
GIVING I
V
TH
t
3
RESULTING IN
THIS VOLTAGE RISING
MORE SLOWLY
RESULTING IN
SLOW RISE OF I
S
Figure 4.
Diagrammatic Representation of Effects
When Switching-ON
Figure 5.
Waveforms at Turn-OFF
At time, t
0
, the drive pulse starts to rise. At t
0
it reaches the threshold voltage of the HEXFET
®
s and the drain current starts to
increase. At this point, two things happen which make the gate-source voltage waveform deviate from its original “path”. First,
inductance in series with the source which is common to the gate circuit (“common source inductance”) develops an induced
voltage as a result of the increasing source current. This voltage counteracts the applied gate drive voltage, and slows down the
rate of rise of voltage appearing directly across the gate and source terminals; this in turn slows down the rate of rise of the
source current. This is a negative feedback effect: increasing current in the source produces a counteractive voltage at the gate,
which tends to resist the change of current.
The second factor that influences the gate-source voltage is the so called “Miller” effect. During the period t
1
to t
2
some voltage
is dropped across “unclamped” stray circuit inductance in series with the drain, and the drain-source voltage starts to fall. The
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Index
AN-937 (v.Int)
decreasing drain-source voltage is reflected across the drain-gate capacitance, pulling a discharge current through it, and
increasing the effective capacitive load on the drive circuit.
This in turn increases the voltage drop across the source impedance of the drive circuit, and decreases the rate of rise of voltage
appearing between the gate and source terminals. Obviously, the lower the impedance of the gate drive circuit, the less this effect
will be. This also is a negative feedback effect; increasing current in the drain results in a fall of drain-to-source voltage, which in
turn slows down the rise of gate-source voltage, and tends to resist the increase of drain current. These effects are illustrated
diagramatically in Figure 4. This state of affairs continues throughout the period t
1
to t
2
, as the current in the HEXFET
®
rises to
the level of the current, I
M
, already flowing in the freewheeling rectifier, and it continues into the next period, t
2
to t
3
, when the
freewheeling rectifier goes into reverse recovery.
Finally, at time t
3
the freewheeling rectifier starts to support voltage and drain current and voltage start to fall. The rate of fall of
drain voltage is now governed almost exclusively by the Miller effect, and an equilibrium condition is reached, under which the
drain voltage falls at just the rate necessary for the voltage between gate and source terminals to satisfy the level of drain current
estab-lished by the load. This is why the gate-to-source voltage falls as the recovery current of the freewheeling rectifier falls,
then stays constant at a level corresponding to the drain current, while the drain voltage falls. Obviously, the lower the impe-
dance of the gate-drive circuit, the higher the discharge current through the drain-gate self-capacitance, the faster will be the fall
time of the drain voltage and the switching
losses.
Finally, at time t
4
, the HEXFET
®
is switched fully
on, and the gate-to-source voltage rises rapidly
towards the applied “open circuit” value.
Similar considerations apply to the turn-off
interval. Figure 5 shows theoretical waveforms
for the HEXFET
®
in the circuit of Figure 4 during
the turn-off interval. At t
o
the gate drive starts to
fall until, at t
l
, the gate voltage reaches a level
that just sustains the drain current and the device
enters the linear mode of operation. The drain-to-
source voltage now starts to rise. The Miller
effect governs the rate-of-rise of drain voltage
and holds the gate-to-source voltage at a level
corresponding to the constant drain current.
Once again, the lower the impedance of the drive
circuit, the greater the charging current into the
drain-gate capacitance, and the faster will be the
rise time of the drain voltage. At t
3
the rise of
drain voltage is complete, and the gate voltage
and drain current start to fall at a rate determined
by the gate-source circuit impedance.
A STEP OF VOLTAGE CAUSES
V
DS
Q
1
We have seen how and why a low gate drive
V
DS
Q
2
impedance is important to achieve high
switching performance. However, even when
A TRANSIENT
switching performance is of no great concern, it
ON THE GATE
is important to minimize the impedance in the
V
GS
Q
1
gate drive circuit to clamp unwanted voltage
transients on the gate. With reference to Figure
6, when one HEXFET
®
is turned on or off, a step
V
GS
Q
2
of voltage is applied between drain and source of
the other device on the same leg. This step of
voltage is coupled to the gate through the gate-to-
Figure 6.
Transients of Voltage Induced on the Gate by Rapid
drain capacitance, and it can be large enough to
Changes on the Drain-to-Source Voltage
turn the device on for a short instant (“dv/dt
induced turn-on”). A low gate drive impedance would keep the voltage coupled to the gate below the threshold.
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AN-937 (v.Int)
In summary:
MOS-gated transistors should be driven from low impedance (voltage) sources, not only to reduce switching losses,
but to avoid dv/dt induced turn-on and reduce the susceptibility to noise.
4. DRIVING STANDARD HEXFET
®
S FROM TTL
Table 1 shows the guaranteed sourcing and sinking currents for different TTL families at their respective voltages. From this
table, taking as an example of the 74LS series, it is apparent that, even with a sourcing current as low as 0.4 mA, the guaranteed
logic one voltage is 2.4V (2.7 for 74LS and 74S). This is lower than the possible threshold of a HEXFET
®
. The use of a pull-up
resistor in the output, as shown in Figure 7, takes the drive voltage up to 5 V, as necessary to drive the gate of Logic Level
HEXFET
®
s, but is not sufficient to fully enhance standard HEXFET
®
s. Section 8 covers the drive characteristics of the logic
level devices in detail.
Logic
Conditions
Logic Zero
Min. sink current
for V
OL
54 / 74
16mA
< 0.4V
54H / 74H
20mA
< (0.4V) /
(54L) /
74L
20mA
< (0.3V) /
0.4V
-0.2mA
>2.4V
50ns
(54LS) /
74LS
(4) / 8
< (0.4V) /
0.5V
-0.4mA
> (2.5) /
2.7V
12ns
74S
20mA
0.5V
-1.0mA
>2.7V
4ns
Logic One
Max. source
current for V
OH
Typical Gate
Propagation Delay
-0.4mA
>2.4V
10ns
-0.5mA
>2.4V
7ns
Table 1.
Driving HEXFET
®
s from TTL (Totem Pole Outputs)
Open collector buffers, like the 7406, 7407, etc., possibly with
several drivers connected in parallel as shown in Figure 9, give
enough voltage to drive standard devices into “full
enhancement”, i.e. data sheet on-resistance. The impedance of
this drive circuit, however, gives relative long switching times.
Whenever better switching performance is required, interface
circuits should be added to provide fast current sourcing and
sinking to the gate capacitances. One simple interface circuit is
the complementary source-follower stage shown in Figure 9. To
drive a MOSFET with a gate charge of 60 nC in 60 ns an average
gate current of 1 A has to be supplied by the gate drive circuit, as
indicated in INT-944. The on-resistance of the gate drive
MOSFETs has to be low enough to support the desired switching
times.
With a gate charge of 60 nC and at a switching frequency is
100kHz, the power lost in the gate drive circuit is approximately:
P = V
GS
x Q
G
x f = 12 x 60 x 10 x 100 x 10 = 72mW
The driver devices must be capable of supplying 1A without
significant voltage drop, but hardly any power is dissipated in
them.
-9
3
PULL-UP
RESISTOR
V
H
TTL
(TOTEM POLE)
LOAD
Figure 7.
Direct Drive from TTL Output
5. DRIVING STANDARD HEXFET
®
S FROM C-MOS
While the same general considerations presented above for TTL would also apply to C-MOS, there are three substantial
differences that should be kept in mind:
1.
C-MOS has a more balanced source/sink characteristic that, on a first approximation, can be thought of as a 500 ohm
resistance for operation over 8V and a 1k ohm for operation under 8V (Table 2).
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