ESS Technology, Inc.
DESCRIPTION
The ES3986 digital-audio processor chip is ESS
Technology’s highly integrated, optimal-quality, and cost-
effective single-chip solution for the emerging digital-audio
market. Its target applications include internet audio
platforms, MP3 CD players in boom box and combination
systems, portable MP3 CD player, etc.
Based on the programmable multimedia processor (PMP)
architecture,
the
ES3986
integrates
software-
configurable 32-bit reduced instruction set computing
(RISC) processor and a 64-bit vector processor core. The
RISC CPU can be used in place of a microcontroller to
provide the functions of system management, user
interface, and peripheral control. The vector processor is
dedicated for audio-specific processing. In addition to
MPEG audio decoding, it will generate 3D sound effects,
and support karaoke features, such as key control and
echo. The chip also provides the voice-activated ADPCM
codec for voice recording and language learning through
MIC input.
The ES3986 supports a variety of CD servos directly to
provide the system solution of lower BOM cost and
manufacturing flexibility. With its low system power
consumption, the built-in antishock capabilities, and 16-
Mbit DRAM support, the ES3986 is very suitable for
portable audio applications.
Figure 1 shows a typical standalone system using a
MP3 player, where the MP3 stream from a CD-ROM is
passed to the ES3986, which parses the system layer
and decodes the audio layer. The decoded MPEG
audio and 3D sound enhancement is then passed to the
external audio DAC.
ES3986
Digital-Audio Processor
Product Brief
FEATURES
•
Programmable multimedia processor (PMP)
architecture
•
MPEG1/MPEG2 and MP3 audio decoder
•
CD block decoder functions
•
STC interpretation and audio phase-lock loop (PLL)
•
256/384 fs for audio system clock
•
Programmable master clock for external audio DAC
•
Independent bit clock for audio transmit and receive
•
Power management
•
2.5V power supply with 5V-tolerant I/Os
•
3D sound and surround sound
•
Karaoke function
•
Vocal reverb: simulates a theater acoustic
environment
•
0.3W power dissipation
•
2-Mb DRAM support
•
100-pin plastic quad flat pack (PQFP) package digital-
audio processor
Remote
Control/
Keypad
Panel
Interface
CD ROM
DRAM
1M x 16
ROM
ES3986
Digital-Audio
Processor
Audio
AUDIO
DAC
Headphones
Amplifier
Figure 1 ES3986 VCD Processor System Block Diagram
ESS Technology, Inc.
SAM0393-031201
1
ES3986 PRODUCT BRIEF
PINOUT
PINOUT
The pinouts for the ES3896 are shown in Figure 2.
LCS0#
LCS1#
LCS3#
LWR#
AUX7
AUX5
AUX6
LOE#
LA11
LA10
VPP
LA12
LA13
LA14
LA15
LA16
LA17
ACLK
AOUT/SEL_PLL0
ATCLK
ATFS/SEL_PLL1
DA9/DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
VSS
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VSS
LD7
LD5
LD4
LD6
LD3
LD2
LD1
LD0
LA9
LA7
LA4
LA1
LA8
LA6
LA5
LA3
LA2
LA0
VSS
AUX4
AUX3
AUX2
AUX1
AUX0
NC
NC
CPUCLK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
ES3986F
100-pin PQFP
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DBUS11
VDD
RAS#
DWE#
DBUS0
DBUS1
DBUS2
DBUS3
DBUS4
DBUS5
DBUS66
DBUS7
DBUS8
DBUS9
DBUS10
DBUS12
DBUS13
DBUS14
DBUS15
Figure 2 ES3986 Pinout Diagram
2
SAM0393-031201
RESET#
VSS
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
ESS Technology, Inc.
ES3986 PRODUCT BRIEF
ES3986 PIN DESCRIPTIONS
ES3986 PIN DESCRIPTIONS
The ES3986 pins are listed and described in Table 1.
Table 1 ES3896 Pin Descriptions
Names
VDD
RAS#
DWE#
DA[8:0]
DBUS[15:0]
RESET#
VSS
NC
CPUCLK
AUX[7:0]
LD[7:0]
LWR#
LOE#
LCS[3,1,0]#
LA[17:0]
VPP
ACLK
AOUT/
SEL_PLL0
Pin Numbers
1, 31, 51
2
3
4:12
13:28
29
30, 50, 80, 100
32:41, 43, 44
42
44:49, 54, 52,
53,
55:62
63
64
65, 66, 67
68:79, 82:87
81
88
89
I/O
I
O
O
O
I/O
I
I
—
I
I/O
I/O
O
O
O
O
I
I/O
O
I
Voltage supply for 2.5V.
DRAM row address strobe (active low).
DRAM write enable (active low).
DRAM multiplexed row and column address bus.
DRAM data bus.
System reset (active low).
Ground.
No Connect.
RISC and system clock input.
CPUCLK is used only if SEL_PLL[1:0] = 00.
Auxiliary control pins (AUX0 and AUX1 are open collectors.)
RISC interface data bus.
RISC interface write enable (active low).
RISC interface output enable (active low).
RISC interface chip select (active low).
RISC interface address bus.
Digital supply voltage for 5V.
Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz)
Dual-purpose pin. AOUT is the audio interface serial data output.
Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK
for the ES3986:
00 = bypass PLL
01 = 54-MHz PLL
10 = 67.5-MHz PLL
11 = 81-MHz PLL.
Audio transmit bit clock.
Dual-purpose pin. ATFS is the audio interface transmit frame sync.
Pins SEL_PLL[1:0] select phase-lock loop clock frequency CPUCLK for the ES3986.
(Refer to the SEL_PLL0 pin above for the settings.)
Dual-purpose pin: DRAM output enable (active low)/DRAM multiplexed row and column
address bus.
Audio interface serial data input.
Audio receive bit clock.
Audio interface receive frame sync.
TDM interface serial clock.
TDM interface serial data receive.
TDM interface frame sync.
DRAM column address strobe bank 0 (active low).
Definitions
ATCLK
ATFS/
SEL_PLL1
90
91
I/O
O
I
DA9/DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
92
93
94
95
96
97
98
99
O
I
I
I
I
I
I
O
ESS Technology, Inc.
SAM0393-031201
3
ES3986 PRODUCT BRIEF
ORDERING INFORMATION
ORDERING INFORMATION
Part Number
ES3986F
Description
Digital-Audio Processor
Package
100-pin PQFP
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
4
No part of this publication may be reproduced, stored in a
retrieval system, transmitted, or translated in any form or
by any means, electronic, mechanical, manual, optical, or
otherwise, without the prior written permission of ESS
Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.
All specifications are subject to change without prior
notice.
ESS Technology, Inc. assumes no responsibility for any
errors contained herein.
(P) U.S. patents pending.
Visba, SmartScale, SmartStream, and
VideoDrive
are
trademarks of ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/
IEC. References to MPEG2 in this document refer to the
ISO/IEC 13818-1.
All other trademarks are owned by their respective
holders and are used for identification purposes only.
© 2001 ESS Technology, Inc. All rights reserved.
SAM0393-031201
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