— Multimedia Codec Port (Interfaces to Philips’ UCB1100
I
Two timer counters
I
208-pin LQFP or 256-ball PBGA packages
I
Evaluation kit available with BOM, schematics,
sample code, and design database
PC Card controllers
I
Support for up to two ultra-low-power CL-PS6700
I
Dedicated LED flasher pin from RTC
I
Full JTAG boundary scan and Embedded ICE
support
1
2
SPI is a registered trademark of Motorola
.
Microwire is a registered trademark of National Semiconductor.
OVERVIEW
(cont.)
Power Management
The EP7211 is designed for ultra-low-power opera-
tion. Its core operates at only 2.5 V, while its I/O has
an operating range of 2.5 V–3.3 V. The device has
three basic power states:
Operating —
This state is the full performance
state. All the clocks and peripheral logic are
enabled.
Idle —
This state is the same as the Operating
State, except the CPU clock is halted while wait-
ing for an event such as a key press.
Standby —
This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key
press can wake up the processor.
Memory Interfaces
There are two main external memory interfaces.
The first one is the ROM/SRAM/Flash-style interface
that has programmable wait-state timings and
includes burst-mode capability, with six chip selects
each decoding 256-Mbyte sections of addressable
space. For maximum flexibility, each bank can be
specified to be 8, 16, or 32 bits wide. This allows the
use of 8-bit-wide boot ROM options to minimize over-
all system cost. The on-chip boot ROM can be used
in product manufacturing to serially download system
code into system Flash memory. To further minimize
system memory requirements and cost, the ARM
Thumb
instruction set is supported, providing for the
2
DS352PP3
JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
OVERVIEW
(cont.)
use of high-speed 32-bit operations in 16-bit op-
codes and yielding industry-leading code density.
The second is the programmable 16- or 32-bit-wide
DRAM interface that allows direct connection of up to
two banks of DRAM, each bank containing up to 256
Mbytes. To assure the lowest possible power con-
sumption, the EP7211 supports self-refresh DRAMs,
which are placed in a low-power state by the device
when it enters the low-power Standby State. EDO
and Fast Page DRAM are supported.
A DMA address generator is also provided that
fetches video display frame buffer data for the LCD
controller from main memory (typically DRAM). The
display frame buffer start address is programmable.
In addition, the built-in LCD controller can utilize
external or internal SRAM for memory, thus eliminat-
ing the need for DRAMs.
Serial Interfaces
The EP7211 includes two 16550-type UARTs for RS-
232 serial communications, both of which have two
16-byte FIFOs for receiving and transmitting data.
The UARTs support bit rates up to 115.2 kbps. An
IrDA SIR protocol encoder/decoder can be optionally
switched into the RX/TX signals to/from one of the
DD[3:0]
CRYSTAL
MOSCIN
CS[4]
PB0
EXPCLK
CL1
CL2
FM
M
COL[7:0]
LCD MODULE
D[31:0]
KEYBOARD
PA[7:0]
PB[7:0]
PD[7:0]
PE[2:0]
PC CARD
SOCKET
CL-PS6700
PC CARD
CONTROLLER
A[27:0]
MOE
WRITE
EP7211
RAS[1]
RAS[0]
×16
DRAM
×16
DRAM
×16
DRAM
×16
DRAM
CAS[0]
CAS[1]
CAS[2]
CAS[3]
CS[0]
CS[1]
POR
PWRFL
BATOK
EXTPWR
BATCHG
RUN
WAKEUP
DRIVE[1:0]
FB[1:0]
SSICLK
SSITXFR
SSITXDA
SSIRXDA
POWER
SUPPLY UNIT
AND
COMPARATORS
DC
INPUT
BATTERY
DC-TO-DC
CONVERTERS
×16
FLASH
×16
FLASH
×16
ROM
×16
ROM
CS[n]
WORD
CODEC
LEDDRV
PHDIN
RXD1/2
TXD1/2
DSR
CTS
DCD
ADCCLK
ADCCS
ADCOUT
ADCIN
SMPCLK
IR LED AND
PHOTODIODE
EXTERNAL MEMORY-
MAPPED EXPANSION
BUFFERS
2× RS-232
TRANSCEIVERS
CS[2]
CS[3]
ADDITIONAL I/O
BUFFERS
AND
LATCHES
ADC
DIGITIZER
Figure 1-1. A EP7211–Based System
DS352PP3
JUL 2001
3
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
OVERVIEW
(cont.)
UARTs to enable these signals to drive an infrared
communication interface directly.
Four synchronous serial interfaces (codec, SSI1,
SSI2, and MCP) are provided. Three of them (codec,
SSI2, and MCP) are multiplexed onto a single set of
interface pins. The full-duplex codec interface allows
direct connection of a standard audio codec chip to
the EP7211, allowing storage and playback of sound.
SSI2 supports both master and slave mode. SSI1
supports master mode only. Both SSI1 and SSI2 sup-
port two industry-standard protocols (SPI
and
Microwire
) for interfacing standard devices (e.g.,
Max148/9 or AD7811/12 ADC), and for allowing
peripheral expansion (e.g., a digitizer pen). A Multi-
media Codec Port (MCP) can be used to communi-
cate with a multi-functional codec device like the
Philips
UCB1100.
System Design
As shown in system block diagram, simply adding
desired memory and peripherals to the highly
integrated EP7211 completes a low-power system
solution. All necessary interface logic is integrated
on-chip.
Development Boards
Cirrus Logic offers an evaluation and development
environment for the EP7211 in the form of the
EDB7211-2 Development Kit.
The EDB7211-2 development kit is a complete devel-
opment platform with access to the features and
capabilities of the EP7211. The kit provides the tools
required for developing and testing the design of a
highly integrated EP7211 system.
Packaging
The EP7211 is available in a 208-pin LQFP package
and a 256-ball PBGA package.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information
describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained
in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express
or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This doc-
ument is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied,
reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written
consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may
be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior
written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent
of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of
their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
4
DS352PP3
JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Main Functional Blocks ...........................................................................................................................35
CPU Core ................................................................................................................................................37
3.3.1 Interrupt Latencies in Different States ........................................................................................39
3.3.1.1 Operating State ..........................................................................................................39
3.3.1.2 Idle State ....................................................................................................................40
3.3.1.3 Standby State .............................................................................................................40
3.4 Memory and I/O Expansion Interface ......................................................................................................42
3.5 EP7211 Boot ROM ..................................................................................................................................43
3.6 CL-PS6700 PC Card Controller Interface ...............................................................................................44
3.7 DRAM Controller with EDO Support .......................................................................................................47
3.8 Serial Interfaces ......................................................................................................................................51
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