Maximum resistance in series with thermal diode that can be
cancelled out
Range over which specified accuracy is achieved. Wider range
can be used with less accuracy.
Using specified thermistor and application circuit over specified
temperature range
V
REF
= 2.25V
30
0.25
±2
100
°C
°C
°C
0
±1
±1
8.30
8.63
35.22
7.93
68.38
87
V
REF
±2.5
±1
8.65
8.99
36.69
8.26
71.24
90.63
V
%
LSB
%/V
ms
ms
ms
ms
ms
ms
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled, Pin 11 and Pin 12 configured for AIN/TH
monitoring (see Table 15)
Averaging enabled, Pin 11 and Pin 12 configured for REM2
monitoring (see Table 15)
±4
65,535
109
329
5000
10000
81.92
%
RPM
RPM
RPM
RPM
kHz
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
Internal Clock Frequency
78.64
85.12
Rev. 0 | Page 3 of 48
ADT7466
Parameter
DRIVE OUTPUTS (DRIVE1, DRIVE2)
Output Voltage Range
Output Source Current
Output Sink Current
DAC Resolution
Monotonicity
Differential Nonlinearity
Integral Nonlinearity
Total Unadjusted Error
REFERENCE VOLTAGE OUTPUT
(REFOUT)
Output Voltage
Output Source Current
Output Sink Current
OPEN-DRAIN SERIAL DATA BUS
OUTPUT (SDA)
Output Low Voltage (V
OL
)
High Level Output Current (I
OH
)
DIGITAL INPUTS (SCL, SDA, TACH
INPUTS, PROCHOT)
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Hysteresis
DIGITAL INPUT CURRENT (TACH
INPUTS, PROCHOT)
Input High Current (I
IH
)
Input Low Current (I
IL
)
Input Capacitance (
IN
)
OPEN-DRAIN DIGITAL OUTPUTS
(ALERT, FANLOCK, FAN1_ON/THERM)
Output Low Voltage (V
OL
)
High Level Output Current (I
OH
)
SERIAL BUS TIMING
2
Clock Frequency (f
SCLK
)
Glitch Immunity (t
SW
)
Bus Free Time (t
BUF
)
Start Setup Time (t
SU;STA
)
Start Hold Time (t
HD;STA
)
SCL Low Time (t
LOW
)
SCL High Time (t
HIGH
)
SCL, SDA Rise Time (t
r
)
SCL, SDA Fall Time (t
f
)
Data Setup Time (t
SU;DAT
)
Detect Clock Low Timeout (t
TIMEOUT
)
1
Min
Typ
0–2.2
2
0.5
Max
Unit
V
mA
mA
Bits
Bits
LSB
LSB
%
Test Conditions/Comments
Digital input = 0x00 to 0xFF
8
8
±1
±1
±5
I
L
= 2 mA
2.226
2.25
2.288
10
0.6
V
mA
mA
0.1
0.4
1
V
µA
I
OUT
= −4.0 mA, V
CC
= 3.3 V
V
OUT
= V
CC
2.0
0.8
0.5
V
V
V
−1
1
20
µA
µA
pF
V
IN
= V
CC
V
IN
= 0
0.1
0.4
1
400
50
V
µA
kHz
ns
µs
µs
µs
µs
µs
ns
ns
ns
Ms
I
OUT
= −4.0 mA, V
CC
= 3.3 V
V
OUT
=V
CC
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
Can be optionally disabled
1.3
0.6
0.6
1.3
0.6
1000
300
100
25
64
All voltages are measured with respect to GND, unless otherwise specified. Typical values are at T
A
= 25°C and represent the most likely parametric norm. Logic inputs
accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of V
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