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EM488M3244VBA-75F

Description
Synchronous DRAM, 8MX32, 5.4ns, CMOS, PBGA90, TFBGA-90
Categorystorage    storage   
File Size194KB,17 Pages
ManufacturerEOREX
Websitehttp://www.eorex.com
Download Datasheet Parametric View All

EM488M3244VBA-75F Overview

Synchronous DRAM, 8MX32, 5.4ns, CMOS, PBGA90, TFBGA-90

EM488M3244VBA-75F Parametric

Parameter NameAttribute value
MakerEOREX
package instructionTFBGA,
Reach Compliance Codeunknown
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresPROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH
JESD-30 codeR-PBGA-B90
length13 mm
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width32
Number of functions1
Number of ports1
Number of terminals90
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8MX32
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height1.14 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width8 mm
Base Number Matches1
eorex
Features
Fully Synchronous to Positive Clock Edge
Single 3.3V
±0.3V
Power Supply
LVTTL Compatible with Multiplexed Address
Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
Programmable CAS Latency (C/L) - 2 or 3
Data Mask (DQM) for Read / Write Masking
Programmable Wrap Sequence
Sequential (B/L = 1/2/4/8/full Page)
Interleave (B/L = 1/2/4/8)
Burst Read with Single-bit Write Operation
All Inputs are Sampled at the Rising Edge of
the System Clock
Auto Refresh and Self Refresh
4,096 Refresh Cycles / 64ms (15.625us)
EM488M3244VBA
256Mb (2M×4Bank×32) Synchronous DRAM
Description
The EM488M3244VBA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages: TFBGA-90B(13mmx8mm).
Ordering Information
Part No
EM488M3244VBA-75F
Organization
8M X 32
Max. Freq
133MHz @CL3
Package
TFBGA -90B
Grade
Commercial
Pb
Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/17
www.eorex.com
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