16-BIT TRI-PORT
BUS EXCHANGER
Integrated Device Technology, Inc.
IDT73720/A
FEATURES:
• High-speed 16-bit bus exchange for interbus communica-
tion in the following environments:
— Multi-way interleaving memory
— Multiplexed address and data busses
• Direct interface to R3051 family RISChipSet™
— R3051™ family of integrated RISController™ CPUs
— R3721 DRAM controller
• Data path for read and write operations
• Low noise 12mA TTL level outputs
• Bidirectional 3-bus architecture: X, Y, Z
— One CPU bus: X
— Two (interleaved or banked) memory busses:Y & Z
— Each bus can be independently latched
• Byte control on all three busses
• Source terminated outputs for low noise and undershoot
control
• 68-pin PLCC and 80-pin PQFP package
• High-performance CMOS technology.
DESCRIPTION:
The IDT73720/A Bus Exchanger is a high speed 16-bit bus
exchange device intended for inter-bus communication in
interleaved memory systems and high performance multi-
plexed address and data busses.
The Bus Exchanger is responsible for interfacing between
the CPU A/D bus (CPU address/data bus) and multiple
memory data busses.
The 73720/A uses a three bus architecture (X, Y, Z), with
control signals suitable for simple transfer between the CPU
bus (X) and either memory bus (Y or Z). The Bus Exchanger
features independent read and write latches for each memory
bus, thus supporting a variety of memory strategies. All three
ports support byte enable to independently enable upper and
lower bytes.
FUNCTIONAL BLOCK DIAGRAM
OEYL
8
LEXY
Y-WRITE
LATCH
16
8
8
LEYX
8
8
OEXL
X
0:7
X
8:15
OEXU
8
8
M
U
16 X
OEXU
OEXL
OEYU
OEYL
OEZU
OEZL
16
Z-READ
LATCH
16
8
Z-WRITE
LATCH
16
8
OEZU
Figure 1. 73720 Block Diagram
NOTE:
1. Logic equations for bus control:
OEXU = T/
R
* .
OEU
*; OEXL = T/
R
* .
OEL
*; OEYU = T/
R
. PATH .
OEU
*
OEYL = T/
R
. PATH .
OEL
*; OEZU = T/
R
. PATH* .
OEU
*; OEZL = T/
R
. PATH* .
OEL
*
RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
Y
0:7
Y
8:15
8
(Even Path)
16
Y-READ
LATCH
OEYU
16
PATH
BUS CONTROL
T/R
OEU
OEL
8
8
LEZX
OEZL
8
8
Z
0:7
Z
8:15
(Odd Path)
2527 drw 01
16
LEXZ
COMMERCIAL TEMPERATURE RANGE
©1995
Integrated Device Technology, Inc.
AUGUST 1995
11.5
DSC-2046/6
1
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
X7
X6
X5
X4
X3
X2
X1
X0
GND
VCC
Z15
Z14
Z13
Z12
Z11
Z10
GND
9
8
7
6
5
4
3
2
GND
X8
X9
X10
X11
X12
X13
X14
X15
GND
VCC
PATH
OEU
LEYX
LEZX
Y0
Y1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
Pin 1
Designator
J68-1
52
51
50
49
48
47
46
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
GND
VCC
LEXZ
OEL
LEXY
T/R
GND
GND
X7
X6
X5
X4
X3
X2
X1
X0
GND
VCC
Z15
Z14
Z13
Z12
Z11
Z10
GND
NC
NC
X8
X9
X10
X11
X12
X13
X14
X15
GND
VCC
PATH
OEU
LEYX
LEZX
Y0
Y1
GND
1
2
3
4
5
6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
NC
NC
GND
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
GND
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
VCC
Y9
Y10
Y11
Y12
Y13
Y14
Y15
2527 drw 02
PLCC
TOP VIEW
Pin 1
Designator
7
8
9
10
11
12
13
14
15
16
17
18
PQ80-1
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
GND
VCC
LEXZ
OEL
LEXY
T/R
NC
NC
GND
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
VCC
Y9
Y10
Y11
Y12
Y13
Y14
Y15
NC
GND
GND
NC
PQFP
TOP VIEW
2527 drw 03
11.5
2
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal
X(0:15)
Y(0:15)
Z(0:15)
LEXY
LEXZ
LEYX
LEZX
PATH
T/
R
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Description
Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus.
Bidirectional Data port Y. Connected to the even path or even bank of memory.
Bidirectional Data port Z. Connected to the odd path or odd bank of memory.
Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXY
Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXZ.
Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even
path Y is latched on the HIGH-to-LOW transition of LEYX.
Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd
path Z is latched on the HIGH-to-LOW transition of LEZX
Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even
path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path).
Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW,
Port X is an output Port while Ports Y & Z are input Ports
Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in
the direction specified by T/
R
.
Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in
the direction specified by T/
R
.
2527 tbl 02
OEU
OEL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
Com’l.
–0.5 to +7.0
Mil.
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, F = 1.0MH
Z
)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
12
Unit
pF
pF
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
–55 to +125
–55 to +125
1.0
50
–55 to +125
–65 to +135
–65 to +125
1.0
50
°C
°C
°C
W
mA
NOTE:
2527 tbl 04
1. This parameter is guaranteed by device characterization, but is not prod-
uction tested.
TRUTH TABLE
Path
L
L
H
H
X
X
X
T/
R
L
H
L
H
X
X
X
OEU
L
L
L
L
H
H
L
OEL
L
L
L
L
H
L
H
Functionality
Z→X (16-bits)–Read Z
(1)
X→Z (16 bits)–Write Z
(1)
Y→X (16-bits)–Read Y
(2)
X→Y (16 bits)–Write Y
(2)
All output buffers are
disabled
Transfer of lower 8 bits
(0:7) as per PATH & T/
R
Transfer of upper 8 bits
(8:15) as per PATH & T/
R
NOTE:
2527 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
2527 tbl 01
1. For Z→X and X→Z transfers, Y-port output buffers are tristated.
2. For Y→X and X→Y transfers, Z-port output buffers are tristated.
11.5
3
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
ARCHITECTURE OVERVIEW
The Bus Exchanger is used to service both read and write
operations between the CPU and the dual memory busses. It
includes independent data path elements for reads from and
writes to each of the memory banks (Y and Z). Data flow
control is managed by a simple set of control signals, analo-
gous to a simple transceiver. In short, the Bus Exchanger
allows bidirectional communication between ports X and Y
and ports X and Z as illustrated in figure 1.
The data path elements for each port include:
Read Latch:
Each of the memory ports Y and Z contains a
transparent latch to capture the contents of the memory bus.
Each latch features an independent latch enable.
Write Latch:
Each memory port Y and Z contains an indepen-
dent latch to capture data from the CPU bus during writes.
Each memory port write latch features an independent latch
enable, allowing write data to be directed to a specific memory
port without disrupting the other memory port.
Data Flow Control Signals
T/
R
(Transmit/
Receive
). This signal controls the direction
of data transfer. A transmit is used for CPU writes, and a
receive is used for read operations.
OEU
,
OEL
are the output enable control signals to select
upper or lower bytes of all three ports.
Path:
The path control signal is used to select between the
even memory path Y and the odd memory path Z during read
or write operations. Path selects the memory port to be
connected to the CPU bus (X-port), and is independent of the
latch enable signals. Thus, it is possible to transfer data from
one memory port to the CPU bus (X) while capturing data from
the other memory port.
element onto the CPU bus, while the first bank is presented
with a new data element.
Transparent Mode
The Bus Exchanger may be used as a data transceiver by
leaving all latches open or transparent.
Memory Write Operations
Memory write operations also consist of two distinct stages.
During one stage, the write data is captured into the selected
memory port write latch. During a later stage, the memory is
presented on the memory port bus
The write operation is selected by driving T/
R
HIGH. Writes
are thus performed using the Path input to select the memory
port (Y or Z). The LEXY/LEXZ capture data in the correspond-
ing Write Latch.
Note that it is possible to utilize the bus exchanger’s write
resources as an additional write buffer, if desired; the CPU
A/D bus can be freed up once the data has been captured by
the Bus Exchanger.
APPLICATIONS
Use as Part of the R3051 Family ChipSet
Figure 2 shows the use of the Bus Exchanger in a typical
R3051 based system.
In write transactions, the R3051 drives data on the CPU
bus. The latch enables are held open through the entire write;
thus, the bus exchanger is used like a transceiver. The
appropriate LEXY/LEXZ signal is derived from ALE (Logic
LOW- indicating that the processor is driving data) and the low
order address bit. The rising edge of
Wr
from the CPU, ends
the write operation.
During read transactions, the memory system is respon-
sible for generating the input control signals to cause data to
be captured at the memory ports. The memory controller is
also responsible for acknowledging back to the CPU that the
data is available, and causing the appropriate path to be
selected.
The R3721 DRAM controller for the R3051 family uses the
transparent latches of the read ports. The R3721 directly
controls the inputs of the bus exchanger, during both reads
and writes. Consult the R3721 data sheet for more informa-
tion on these control signals.
Use in a general 32-bit System
Figures 3 and 4 illustrate the use of the Bus Exchanger in
a 32-bit microprocessor based system. Note the reduced pin
count achieved with the Bus Exchanger.
MEMORY READ OPERATIONS
Latch Mode
In this mode the read operation consists of two stages.
During the first stage, the data present at the memory port is
captured by the read latch for that memory port. During a
subsequent stage, data is brought from a selected memory
port to the CPU A/D port X by using output enable control.
The read operation is selected by driving T/
R
LOW. The
read is managed using the Path input to select the memory
port (Y or Z); the LEYX/LEZX enable the data capture into the
corresponding Read Latch.
In this way, memory interleaving can be performed. While
data from one bank is output onto the CPU bus, data on the
other bank is captured in the other memory port. In the next
cycle, the Path input is changed, enabling the next data
11.5
4
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
Clk2xIn
IDT R3051 FAMILY
RISController
ADDRESS/DATA
R305x
LOCAL BUS
CONTROL
IDT79R3721
DRAM
CONTROLLER
DRAM
DRAM
IDT73720
BUS EXCHANGER
(2)
Figure 2. Bus Exchanger Used in R3051 Family System
2527 drw 04
CPU
32
4 x (74FCT373)
2 x (73720)
CPU
32
4 x (74FCT373)
2 x (73720)
DRAM 1
Address
Data Bus Chip Count = 2 Pin Count = 136
DRAM 2
DRAM 1
Address
Data Bus Chip Count = 2 Pin Count = 136
DRAM 2
CPU
32
CPU
32
4 x (74FCT373)
4 x (74FCT245)
4 x (74FCT245)
4 x (74FCT373)
4 x (74FCT543)
4 x (74FCT543)
DRAM 1
Address
Data Bus Chip Count = 8 Pin Count = 160
DRAM 2
DRAM 1
Address
Data Bus Chip Count = 8 Pin Count = 192
DRAM 2
2527 drw 05
2527 drw 06
Figure 3. CPU System with Transparent Data Path
(2-way Interleaving)
11.5
Figure 4. CPU System with Latched Data Path
(2-way Interleaving)
5
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