VVZ40-12io1
Thyristor \ Diode Module
3~
Rectifier
V
RRM
= 1200 V
I
DAV
=
I
FSM
=
45 A
320 A
3~ Rectifier Bridge, half-controlled (high-side)
Part number
VVZ40-12io1
Backside: isolated
8
4
7
5
1
6
3
2
Features / Advantages:
●
Package with DCB ceramic base plate
●
Improved temperature and power cycling
●
Planar passivated chips
●
Very low forward voltage drop
●
Very low leakage current
Applications:
●
Line rectifying 50/60 Hz
●
Drives
●
SMPS
●
UPS
Package:
V1-B-Pack
●
Isolation Voltage: 3600 V~
●
Industry standard outline
●
RoHS compliant
●
Soldering pins for PCB mounting
●
Height: 10 mm
●
Base plate: DCB ceramic
●
Reduced weight
●
Advanced power cycling
Terms and Conditions of Usage
The data contained in this product data sheet is exclusively intended for technically trained staff. The user will have to evaluate the suitability of the product for the intended application and
the completeness of the product data with respect to his application. The specifications of our components may not be considered as an assurance of component characteristics. The
information in the valid application- and assembly notes must be considered. Should you require product information in excess of the data given in this product data sheet or which concerns
the specific application of your product, please contact your local sales office.
Due to technical requirements our product may contain dangerous substances. For information on the types in question please contact your local sales office.
Should you intend to use the product in aviation, in health or life endangering or life support applications, please notify. For any such application we urgently recommend
- to perform joint risk and quality assessments;
- the conclusion of quality agreements;
- to establish joint measures of an ongoing product survey, and that we may make delivery dependent on the realization of any such measures.
IXYS reserves the right to change limits, conditions and dimensions.
Data according to IEC 60747and per semiconductor unless otherwise specified
20140310e
© 2014 IXYS all rights reserved
VVZ40-12io1
Rectifier
Symbol
V
RSM/DSM
V
RRM/DRM
I
R/D
V
T
Definition
Conditions
T
VJ
= 25°C
T
VJ
= 25°C
T
VJ
= 25°C
T
VJ
= 125°C
T
VJ
= 25°C
T
VJ
= 125 °C
T
VJ
= 125 °C
d=
⅓
T
VJ
= 125 °C
0.85
15
0.60
T
C
= 25°C
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
I²t
value for fusing
Ratings
min.
typ.
max. non-repetitive reverse/forward blocking voltage
max. repetitive reverse/forward blocking voltage
reverse current, drain current
forward voltage drop
max. Unit
1300
V
1200
300
5
1.12
1.47
1.07
1.52
45
V
µA
mA
V
V
V
V
A
V
mΩ
K/W
100
320
345
270
295
510
495
365
360
W
A
A
A
A
A²s
A²s
A²s
A²s
pF
10
1
0.5
W
W
W
V
R/D
= 1200 V
V
R/D
= 1200 V
I
T
=
I
T
=
I
T
=
I
T
=
15 A
45 A
15 A
45 A
I
DAV
V
T0
r
T
R
thJC
R
thCH
P
tot
I
TSM
bridge output current
T
C
= 100 °C
rectangular
threshold voltage
slope resistance
for power loss calculation only
thermal resistance junction to case
thermal resistance case to heatsink
total power dissipation
max. forward surge current
1 K/W
T
VJ
= 45°C
V
R
= 0 V
T
VJ
= 125 °C
V
R
= 0 V
T
VJ
= 45°C
V
R
= 0 V
T
VJ
= 125 °C
V
R
= 0 V
T
VJ
= 25°C
T
C
= 125 °C
16
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
C
J
P
GM
P
GAV
(di/dt)
cr
junction capacitance
max. gate power dissipation
V
R
= 400 V f = 1 MHz
t
P
= 30 µs
t
P
= 300 µs
average gate power dissipation
critical rate of rise of current
T
VJ
= 125 °C; f = 50 Hz
repetitive, I
T
=
t
P
= 200 µs; di
G
/dt = 0.3 A/µs;
I
G
=
0.3 A; V =
⅔
V
DRM
non-repet., I
T
=
V =
⅔
V
DRM
R
GK
=
∞; method 1 (linear voltage rise)
V
D
= 6 V
V
D
= 6 V
V
D
=
⅔
V
DRM
t
p
=
I
G
=
30 µs
0.3 A; di
G
/dt =
0.3 A/µs
45 A
15 A
150 A/µs
500 A/µs
1000 V/µs
1
1.2
65
80
0.2
5
150
100
2
150
V
V
mA
mA
V
mA
mA
mA
µs
µs
(dv/dt)
cr
V
GT
I
GT
V
GD
I
GD
I
L
I
H
t
gd
t
q
critical rate of rise of voltage
T
VJ
= 125°C
T
VJ
= 25 °C
T
VJ
= -40 °C
T
VJ
= 25 °C
T
VJ
= -40 °C
T
VJ
= 125°C
T
VJ
= 25 °C
T
VJ
= 25 °C
T
VJ
= 25 °C
0.3 A/µs
20 V/µs t
p
= 300 µs
gate trigger voltage
gate trigger current
gate non-trigger voltage
gate non-trigger current
latching current
holding current
gate controlled delay time
V
D
= 6 V R
GK
=
∞
V
D
= ½ V
DRM
I
G
=
0.3 A; di
G
/dt =
turn-off time
V
R
= 100 V; I
T
= 15 A; V =
⅔
V
DRM
T
VJ
=100 °C
di/dt = 10 A/µs dv/dt =
IXYS reserves the right to change limits, conditions and dimensions.
Data according to IEC 60747and per semiconductor unless otherwise specified
20140310e
© 2014 IXYS all rights reserved
VVZ40-12io1
Package
Symbol
I
RMS
T
VJ
T
op
T
stg
Weight
M
D
d
Spp/App
d
Spb/Apb
V
ISOL
isolation voltage
t = 1 second
t = 1 minute
50/60 Hz, RMS; I
ISOL
≤
1 mA
mounting torque
creepage distance on surface | striking distance through air
terminal to terminal
terminal to backside
V1-B-Pack
Definition
RMS current
virtual junction temperature
operation temperature
storage temperature
Ratings
Conditions
per terminal
min.
-40
-40
-40
typ.
max.
100
125
100
125
Unit
A
°C
°C
°C
g
Nm
mm
mm
V
V
30
2
6.0
12.0
3600
3000
2.5
Date Code
Prod. Index
yywwA
Part Number (Typ)
Lot No.:
Data Matrix:
Typ
(1-19), DC+Prod.Index (20-25),
FKT#
(26-31)
leer
(33),
lfd.#
(33-36)
Ordering
Standard
Ordering Number
VVZ40-12io1
Marking on Product
VVZ40-12io1
Delivery Mode
Box
Quantity
5
Code No.
466352
Equivalent Circuits for Simulation
I
V
0
R
0
threshold voltage
slope resistance *
Thyristor
* on die level
T
VJ
= 125 °C
V
0 max
R
0 max
0.85
12.5
V
mΩ
IXYS reserves the right to change limits, conditions and dimensions.
Data according to IEC 60747and per semiconductor unless otherwise specified
20140310e
© 2014 IXYS all rights reserved
VVZ40-12io1
Outlines V1-B-Pack
2
31
Kühlfläche
cooling area
35 x 26
38.6
14
5 5
2
1
3
4
14
11
0.5
5.3
1.6
48
63
8
4
7
5
1
6
3
5.3
2
11
6
7
IXYS reserves the right to change limits, conditions and dimensions.
5
8
Data according to IEC 60747and per semiconductor unless otherwise specified
27.2
31.6
ca. 0.25
10
2
20140310e
© 2014 IXYS all rights reserved
VVZ40-12io1
Thyristor
60
50
40
T
VJ
= 45°C
300
600
500
400
I
F
30
I
FSM
T
VJ
= 125°C
T
VJ
= 25°C
It
200
300
2
T
VJ
= 45°C
[A]
20
10
[A]
[A s]
T
VJ
= 125°C
200
100
50Hz, 80% V
RRM
100
0.001
0
0.01
0.1
1
1
2
T
VJ
= 125°C
0
0.0
0.5
1.0
1.5
2.0
2
2
3
4 5 6 7 89
V
F
[V]
Fig. 1 Forward current vs.
voltage drop per thyristor
10
1000
t [s]
Fig. 2 Surge overload current
vs. time per thyristor
60
50
6
t [ms]
Fig. 3 I t vs. time per thyristor
1: I
GD
, T
VJ
= 125°C
2: I
GT
, T
VJ
= 25°C
3: I
GT
, T
VJ
= -40°C
T
VJ
= 25°C
typ.
Limit
V
G
1
4
2 3
5
100
40
t
gd
[μs]
10
I
T(AV)M
30
DC =
1
0.5
0.4
0.33
0.17
0.08
[V]
1
4: P
GAV
= 0.5 W
5: P
GM
= 1 W
6: P
GM
= 10 W
[A]
20
10
1
10
0
100
1000
0
50
100
150
0.1
10
0
10
1
10
2
10
3
10
4
I
G
[mA]
Fig. 4 Gate trigger characteristics
I
G
[mA]
Fig. 5 Gate trigger delay time
T
C
[°C]
Fig. 5 Max. forward current vs.
case temperature per thyristor
25
DC =
1
0.5
20
0.4
0.33
0.17
15
0.08
1.2
R
thHA
:
0.6 K/W
0.8 K/W
1.0 K/W
2.0 K/W
4.0 K/W
8.0 K/W
1.0
0.8
P
tot
[W]
10
5
Z
thJC
0.6
Constants for Z
thJC
calc.:
i
1
2
3
4
5
1
10
100
[K/W]
0.4
0.2
0.0
0
5
10
15
20
0
50
100
150
R
th
(K/W)
0.020
0.100
0.210
0.410
0.260
1000
t
i
(s)
0.0004
0.0090
0.0140
0.0500
0.3600
10000
0
I
T(AV)M
[A]
T
amb
[°C]
t [ms]
Fig. 6 Transient thermal impedance junction to case
vs. time per thyristor
Data according to IEC 60747and per semiconductor unless otherwise specified
20140310e
Fig. 4 Power dissipation vs. forward current
and ambient temperature per thyristor
IXYS reserves the right to change limits, conditions and dimensions.
© 2014 IXYS all rights reserved
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