UTC 3511
PC POWER SUPPLY
SUPERVISORS
DESCRIPTION
The UTC 3511 provides protection circuits, power
good output (PGO), fault protection latch (FPL_N),
and protection detector function (PDON_N) control.
It can minimize external components of switching
power supply systems in personal computer.
The Over Voltage Detector (OVD) monitors 3.3V,
5V, 12V input voltage level. The Under Voltage
Detector (UVD) monitors 3.3V, 5V input voltage level.
When OVD or UVD detect the fault voltage level, the
FPL_N is latched HIGH and PGO goes LOW. The
latch can be reset by PDON_N going HIGH. There is
2.4ms delay time for PDON_N turning off FPL_N.
When OVD and UVD detect the right voltage level,
the power good output (PGO) will be issue.
CMOS IC
SOP-8
DIP-8
FEATURES
* The Over Voltage Detector (OVD) monitors
3.3V, 5V, 12V input voltage level.
* The Under Voltage Detector (UVD) monitors 3.3V,
5V input voltage level.
* Both of the power good output (PGO) and the fault
protection latch (FPL_N) are Open Drain Output.
* 75 ms time delay for UVD.
* 300 ms time delay for PGO.
* 38 ms for PDON_N input signal De-bounce.
* 73 us for internal signal De-glitches.
* 2.4 ms time delay for PDON_N turn-off FPL_N.
PIN CONFIGURATION
PGI
GND
FPL_N
PDON_N
1
2
3
4
8
7
6
5
PGO
VDD
V5
V33
UTC
UNISONIC TECHNOLOGIES CO., LTD.
1
QW-R502-015,B
UTC 3511
PIN DESCRIPTION
PIN No.
PIN NAME
1
PGI
2
3
4
5
6
7
8
GND
FPL-N
PDON-N
V33
V5
VDD
PGO
CMOS IC
TYPE
I
P
O
I
I
I
I
O
Power good input pin
Ground
Fault protection latch output pin (open drain output)
Protection detector function ON/OFF control input pin
3.3V input pin
5V input pin
Supply voltage/12V input pin
Power good output pin(open drain output)
DESCRIPTION
BLOCK DIAGRAM
V
DD
150uA
3.6V
Power On Reset
Vcc Low Voltage
POR
LVRST
Clock
Generator
CLK
PWR
CLK
CLK
PWR
RST
PWR
PDON_N
38ms
debounce
-
CLR
2.4ms
delay
V33
UN
+
CLK
RWR
-
OV
+
-
V5
UN
+
CLR 75ms
delay
CLK
RST
R
FPL_N
-
OV
+
73us
debounce
S Q
V
DD
-
OV
+
V
DD
CLK RST
73us
debounce
CLK
PGO
-
PGI
UN
+
CLR
300ms
delay
1.2V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage
Input Voltage
Output Voltage
PDON_N,V5,V33,PGI
FPL_N
PGO
SYMBOL
V
DD
Vin
V
OUT
RATINGS
-0.3 ~ 16
-0.3 ~ 7
-0.3 ~ 16
-0.3 ~ 7
-40 ~ 125
-55 ~ 150
UNIT
V
V
V
°C
°C
Operating temperature
Topr
Storage temperature
Tstg
Note:Stresses above those listed may cause permanent damage to the devices
UTC
UNISONIC TECHNOLOGIES CO., LTD.
2
QW-R502-015,B
UTC 3511
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Output Sink Current
Supply Voltage Rising Time
PDON_N,V5,V33,PGI
FPL_N
PGO
FPL_N
PGO
CMOS IC
SYMBOL
V
DD
Vin
V
OUT
Iosink
Trs
1
MIN
3.8
TYP
12
MAX
15
7
15
7
30
10
UNIT
V
V
V
V
mA
mA
ms
ELECTRICAL CHARACTERISTICS
(Ta=25℃, V
DD
=5V)
Over Voltage Detection
PARAMETER
Over voltage threshold
SYMBOL
TEST CONDITIONS
MIN
3.7
5.7
12.8
TYP.
3.9
6.1
13.4
5
0.3
0.7
MAX
4.1
6.5
13.9
UNIT
V
uA
V
Leakage current (FPL_N)
Low level output voltage
(FPL_N)
V33
V5
V
DD
/ V12
I
LEAKAGE
FPL_N=5V
I
sink
=10mA
V
OL
I
sink
=30mA
PGI and PGO
PARAMETER
Under voltage threshold
Input threshold voltage (PGI)
Leakage current (PGO)
Low level output voltage (PGO)
SYMBOL
V33
V5
TEST CONDITIONS
MIN
2.55
4.1
1.16
TYP.
2.69
4.3
1.20
5
0.4
MAX
2.83
4.47
1.24
UNIT
V
uA
V
V
PGI
I
LEAKAGE
PGO=5V
V
OL
I
sink
=10mA
PDON_N
PARAMETER
Input pull-up current
High-level input voltage
Low-level input voltage
SYMBOL
I
l
V
IH
V
IL
TEST CONDITIONS
PDON_N=0V
MIN
2.4
TYP.
150
MAX
UNIT
uA
V
V
1.2
TOTAL DEVICE
PARAMETER
Supply current
low voltage
SYMBOL
Icc
V
DD
TEST CONDITIONS
PDON_N=5V
MIN
TYP.
3
MAX
1
UNIT
mA
V
UTC
UNISONIC TECHNOLOGIES CO., LTD.
3
QW-R502-015,B
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