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FMS7951
Zero Delay Clock Multiplier
Features
•
•
•
•
•
•
•
•
•
Low Voltage CMOS or PECL reference input
Up to 175 MHz of output frequency
Nine configurable outputs
Output enable pin
250 pS of output to output skew
300 pS of Cycle to Cycle Jitter
V
DD
Range of 3.3V ±0.2V
Commercial temperature range
Available in 32 pin TQFP
It has four banks of configurable outputs. By externally con-
necting one of the outputs to FBIN, the internal PLL will
lock in both phase and frequency to the incoming clock. Any
changes to the input clock will be tracked by the outputs.
Depending on the selected output for feedback connection,
the output frequencies will be as 1X, 2X or 4X of the input.
REF_SEL allows selection between PECL input or TCLK a
CMOS clock driven input. Connecting PLL_EN LOW and
REF_SEL HIGH will by pass the Phase locked loop. In this
mode, FMS7951 will be in clock buffer mode where any
clock applied to TCLK will be divided down to the four out-
put banks. This is ideal for system diagnostic test. When
PLL_EN is HIGH, the PLL is enabled, and any clock applied
to TCLK will be locked in both phase and frequency to
FBIN. PECL_CLK is activated when REF_SEL is high.
FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP.
Description
FMS7951 is a high speed, zero delay, low skew clock driver. It
uses phase locked loop technology to generate frequencies up
to 175 MHz.
Block Diagram
REF_SEL
PLL_EN
OE
TCLK
QA
MUX
MUX
PECL_CLK
PECL_CLK
FBIN
QC1
QD0
QD1
DIV_SEL A
QD2
DIV_SEL B
DIV_SEL C
DIV_SEL D
QD4
Control
Logic
PLL
QC0
QB
QD3
REV. 1.0.0 1/9/01
PRODUCT SPECIFICATION
FMS7951
Pin Assignments
REF_SEL
GNDOUT
QA
VDDOUT
GNDOUT
PLL_EN
TCLK
VDDCOR
FBIN
DIV_SEL A
DIV_SEL B
DIV_SEL C
DIV_SEL D
GNDCOR
PECL_CLK
32 31 30 29 28 27 26 25
24
1
2
23
3
4
5
6
7
8
9 10 11 12 13 14 15 16
PECL_CLK
OE
GNDOUT
VDDOUT
QD3
VDDOUT
QD4
QD2
22
32-PIN
LQFP
21
20
19
18
17
QB
QC0
VDDOUT
QC1
GNDOUT
QD0
VDDOUT
QD1
GNDOUT
Pin Description
Pin Name
VDDCOR
FBIN
DIV_SEL(A:D)
GNDCOR
PECL_CLK/
PECL_CLK
OE
VDDOUT
Pin #
1
2
3, 4, 5, 6
7
8, 9
10
11, 15, 19, 23, 27
Pin Type
PWR
IN
IN
PWR
IN
IN
PWR
OUT
PWR
IN
IN
IN
Description
Power Connection.
Power supply for core logic and PLL
circuitry. Connect to 3.3 Volts nominal.
Feedback In.
PLL feedback input. The user connects it to one of
the outputs.
Divider Select:
It divides the clock to a desirable value. See
table 2. No internal pull up or pull down.
Ground Connection.
Ground for core logic and PLL circuitry.
Connect to the common system ground plane.
PECL Clock Input:
These are differential PECL inputs when
REF_SEL is Low, they are activated.
Output Enable.
When high, all outputs are in high impedance.
Normal operation when asserted low.
Power Connection.
Power supply for all the output buffers.
Connect to 3.3 Volts nominal.
Clock Outputs.
These outputs are multiple of the input.
Ground Connection.
Ground for all the outputs. Connect to
common system ground plane.
Test Clock.
When PLL-EN is low, all outputs are buffer copy of
TCLK.
PLL Enable.
When low, PLL is by passed.
Reference Select.
When low, PECL_CLK/PECL_CLK is used
for input. When high, TCLK is used for input.
Q
A
; Q
B
; Q
C
(0:1); 12, 14, 16, 18, 20,
Q
D
(0:4)
22, 24, 26, 28
GNDOUT
TCLK
PLL_EN
REF_SEL
13, 17, 21, 25, 29
30
31
32
2
REV. 1.0.0 1/9/01
FMS7951
PRODUCT SPECIFICATION
Table 1. Functionality
REF_SEL
0
0
0
1
1
1
PLL_EN
0
0
1
0
0
1
OE
1
0
0
1
0
0
PLL
By Pass
By Pass
Enabled
By Pass
By Pass
Enabled
All Outputs
Hi-Z
Running
Running
Hi-Z
Running
Running
Input
PECL_CLK
PECL_CLK
PECL_CLK
TCLK
TCLK
TCLK
Table 2. Input Versus Output Frequency
DIV_SELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DIV_SELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DIV_SELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIV_SELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QA
2XREF
4XREF
2XREF
4XREF
2XREF
4XREF
2XREF
4XREF
REF
2XREF
REF
2XREF
REF
2XREF
REF
2XREF
QB
REF
2XREF
REF
2XREF
1/2REF
REF
1/2REF
REF
REF
2XREF
REF
2XREF
1/2REF
REF
1/2REF
REF
QC
REF
2XREF
1/2REF
REF
REF
2XREF
1/2REF
REF
REF
2XREF
1/2REF
REF
REF
2XREF
1/2REF
REF
QD
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note:
1. Reference input could be either PECL_CLK or TCLK input.
2. FBIN is tied to QD output for table
Table 3. Divide Select Functionality
DIV_SEL A
0
1
DIV_SEL B
0
1
DIV_SEL D
0
1
DIV_SEL D
0
1
QA
÷
2
÷
4
QB
÷
4
÷
8
QC
÷
4
÷
8
QD
÷
4
÷
8
REV. 1.0.0 1/9/01
3
PRODUCT SPECIFICATION
FMS7951
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
B
T
A
Parameter
Voltage on any pin with respect to ground
Storage Temperature
Ambient Temperature
Operating Temperature
Ratings
-0.5 to 7.0
-65 to 150
-55 to 125
0 to 70
Units
V
°C
°C
°C
Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may effect reliability.
DC Electrical Characteristics
T
A
= 0 to 70°C; Supply Voltage 3.3 V ±0.2V (unless otherwise stated)
Parameter
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Peak to Peak Input
Voltage
Common Mode Range
Output Low Voltage
Output High Voltage
Input
Clock
Capacitance
(1)
Stabilization
(1)
Supply Current
Symbol
V
IL
V
IH
I
IL
I
IH
V
PP
V
CMR
V
OL
V
OH
C
IN
I
DD
T
STAB
Outputs loaded
From V
DD
= 3.3V to 1% Target
TBD
I
OL
= 40 mA
I
OH
= –40mA
2.2
7.0
150
10
Conditions
TCLK; control pins
TCLK; control pins
V
IN
= 0
V
IN
= V
DD
PECL_CLK/PCL_CLK
2.0
-10
-30
0.3
V
DD
-2.0
Min.
Typ.
Max.
0.8
3.6
10
30
1.0
V
DD
-0.6
0.5
Units
V
V
µA
µA
V
mV
V
V
pF
mA
mS
Note:
1. Guaranteed by design, not subject to 100% production testing.
AC Electrical Characteristics
T
A
= 0 to 70°C; Supply Voltage V
DD
= 3.3V ±0.2V, C
L
= 10 pF (unless otherwise stated)
Parameter
Input Frequency
Symbol
F
IN
Conditions
Feedback Divide = 2
Feedback Divide = 4
Feedback Divide = 8
TCLK Input Rise/Fall Time
(1)
TCLK Input Duty Cycle
(1)
Output Frequency Range
T
R_IN
/T
F_IN
D
T_IN
F
OUT
Q
A
; DIV_SEL A = 0V
Q
B
, Q
C
& Q
D
;
DIV_SEL B, C, D = 0V
Output to Output Skew
Input to FBIN Delay
T
SK1
T
SK2
V
TH
= V
DD
/2; DIV_SEL A = 0
V
TH
= V
DD
/2; DIV_SEL A = 1
TCLK
PECL_CLK
-300
50
-950
Min.
10
10
10
–
25
Typ.
Max.
175
85
42
3.0
75
175
88
750
300
400
-600
pS
ns
%
MHz
MHz
pS
Units
MHz
4
REV. 1.0.0 1/9/01
FMS7951
PRODUCT SPECIFICATION
AC Electrical Characteristics
(Cont.)
T
A
= 0 to 70°C; Supply Voltage V
DD
= 3.3V ±0.2V, C
L
= 10 pF (unless otherwise stated)
Parameter
Rise Time
(1)
Fall Time
(1)
Duty Cycle
(1)
Jitter (Cycle-Cycle)
Symbol
T
R
T
F
D
T
T
JIT
Conditions
0.8 to 2.0V
2.0 to 0.8V
V
TH
= V
DD
/2
QA: DIV_SEL A = 0
QA: DIV_SEL A = 1
QB Output
QC(0:1) Outputs
QD(0:4) Outputs
Note:
1. Guaranteed by design, not subject to 100% production testing.
Min.
0.10
0.10
45
Typ.
Max.
1.0
1.0
55
450
200
200
300
375
Units
nS
nS
%
pS
REV. 1.0.0 1/9/01
5
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