STE48NM60
N-CHANNEL 650V @ Tjmax - 0.09Ω - 48A ISOTOP
MDmesh™ MOSFET
Table 1: General Features
TYPE
STE48NM60
s
s
s
s
Figure 1: Package
R
DS(on)
< 0.11Ω
I
D
48 A
V
DSS
(
@
Tjmax)
650V
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TYPICAL R
DS
(on) = 0.09Ω
HIGH dv/dt AND AVALANCHE CAPABILITIES
100% AVALANCHE TESTED
LOW INPUT CAPACITANCE AND GATE
CHARGE
LOW GATE INPUT RESISTANCE
TIGHT PROCESS CONTROL AND HIGH
MANUFACTURING YIELDS
s)
t(
ISOTOP
DESCRIPTION
The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain pro-
cess with the Company’s PowerMESH™ horizon-
tal layout. The resulting product has an
outstanding low on-resistance, impressively high
dv/dt and excellent avalanche characteristics. The
adoption of the Company’s proprietary strip tech-
nique yields overall dynamic performance that is
significantly better than that of similar competi-
tion’s products.
Figure 2: Internal Schematic Diagram
APPLICATIONS
The MDmesh™ family is very suitable for increas-
ing power density of high voltage converters allow-
ing system miniaturization and higher efficiencies.
Table 2: Order Codes
SALES TYPE
STE48NM60
MARKING
E48NM60
PACKAGE
ISOTOP
PACKAGING
TUBE
Rev. 2
March 2005
1/9
STE48NM60
Table 3: Absolute Maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
( )
P
TOT
dv/dt (1)
V
ISO
T
stg
T
j
Gate- source Voltage
Drain Current (continuous) at T
C
= 25°C
Drain Current (continuous) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
Peak Diode Recovery voltage slope
Insulation Winthstand Voltage (AC-RMS)
Storage Temperature
Max. Operating Junction Temperature
Parameter
Value
±30
48
30
192
450
3.57
15
2500
–65 to 150
150
Unit
V
A
A
A
W
W/°C
V/ns
V
°C
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( )
Pulse width limited by safe operating area
(1) I
SD
≤
48A, di/dt
≤
400 A/µs, V
DD
≤
V
(BR)DSS
, T
j
≤
T
JMAX.
°C
s)
t(
Table 4: Thermal Data
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Max
0.28
30
300
°C/W
°C/W
°C
Thermal Resistance Junction-ambient
Max
Maximum Lead Temperature For Soldering Purpose
(*) with conductive GREASE Applies
Table 5: Avalanche Characteristics
Symbol
I
AR
Parameter
Max Value
15
Unit
A
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 35 V)
E
AS
850
mJ
ELECTRICAL CHARACTERISTICS
(T
CASE
=25°C UNLESS OTHERWISE SPECIFIED)
Table 6: On/Off
Symbol
Parameter
Test Conditions
Min.
600
Typ.
V
(BR)DSS
I
DSS
Drain-source
Breakdown Voltage
I
D
= 250 µA, V
GS
= 0
V
DS
= Max Rating
Max.
Unit
V
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
10
µA
V
DS
= Max Rating, T
C
= 125°C
100
µA
nA
V
Ω
I
GSS
V
GS
= ±30V
±100
5
V
GS(th)
Gate Threshold Voltage
Static Drain-source On
Resistance
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 22.5A
3
4
R
DS(on)
0.09
0.11
2/9
STE48NM60
ELECTRICAL CHARACTERISTICS
(CONTINUED)
Table 7: Dynamic
Symbol
g
fs
(1)
C
iss
C
oss
C
rss
C
oss eq.
(2)
R
G
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Equivalent Output
Capacitance
Gate Input Resistance
Test Conditions
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 24A
V
DS
= 25V, f = 1 MHz, V
GS
= 0
Min.
Typ.
20
3800
1250
80
340
1.4
Max.
Unit
S
pF
pF
pF
pF
Ω
V
GS
= 0V, V
DS
= 0V to 480V
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
V
DD
= 250V, I
D
= 22.5A R
G
= 4.7Ω
V
GS
= 10V
(see Figure 14)
V
DD
= 400V, I
D
= 45A, R
G
= 4.7Ω,
V
GS
= 10V
V
DD
= 400V, I
D
= 45A,
V
GS
= 10V
(see Figure 18)
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t
r(Voff)
t
f
t
c
Q
g
Q
gs
Q
gd
Off-voltage Rise Time
Fall Time
Cross-over Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
16
23
40
96
31
43
134
t
d(on)
t
r
Turn-on Delay Time
Rise Time
30
20
ns
ns
s)
t(
ns
ns
ns
nC
nC
nC
Table 8: Source Drain Diode
Symbol
I
SD
I
SDM
(2)
V
SD
(1)
t
rr
Q
rr
t
rr
Q
rr
Parameter
Test Conditions
Min.
Typ.
Max.
48
Unit
A
A
V
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
192
1.5
I
SD
= 45A, V
GS
= 0
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 45A, di/dt = 100A/µs,
V
DD
= 100 V, T
j
= 25°C
(see Figure 16)
I
SD
= 45A, di/dt = 100A/µs,
V
DD
= 100 V, T
j
= 150°C
(see Figure 16)
508
10
40
650
14
43
ns
µC
A
ns
µC
A
I
RRM
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
3/9
STE48NM60
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
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Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
s)
t(
Figure 8: Static Drain-source On Resistance
4/9
STE48NM60
Figure 9: Gate Charge vs Gate-source Voltage
Figure 12: Capacitance Variations
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Figure 10: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 11: Source-Drain Diode Forward Char-
acteristics
s)
t(
Figure 13: Normalized On Resistance vs Tem-
perature
5/9
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