21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT573
Fast CMOS 3.3V 8-Bit
Transparent Latch
Features
• Compatible with LCX™ and LVT™ families of products
• Supports 5V Tolerant Mixed Signal Mode Operation
– Input can be 3V or 5V
– Output can be 3V or connected to 5V bus
• Advanced Low Power CMOS Operation
• Excellent output drive capability:
Balanced drives (24 mA sink and source)
• Low ground bounce outputs
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 20-pin 173 mil wide plastic TSSOP (L)
– 20-pin 150 mil wide plastic QSOP (Q)
– 20-pin 150 mil wide plastic TQSOP (R)
– 20-pin 300 mil wide plastic SOIC (S)
Description
Pericom Semiconductor’s PI74LPT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74LPT573 is an 8-bit transparent latch designed with
3-state outputs and is intended for bus oriented applications. When
Latch Enable (LE) is HIGH, the flip-flops appear transparent to the
data. The data that meets the set-up time when LE is LOW is latched.
When OE is HIGH, the bus output is in the high impedance state.
The PI74LPT573 can be driven from either 3.3V or 5.0V devices
allowing this device to be used as a translator in a mixed
3.3/5.0V system.
Logic Block Diagram
Pinout
OE
LE
D
0
D
O
G
O
0
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
20
1
19
2
18
3
20-Pin
17
4
L20
16
5
R20
15
6
Q20
7
S20
14
13
8
12
9
11
10
Vcc
O0
O1
O2
O3
O4
O5
O6
O7
LE
TO 7 OTHER CHANNELS
Truth Table
D
N
H
L
X
Inputs
(1)
LE
H
H
X
OE
L
L
H
Outputs
(1)
O
N
H
L
Z
Pin Description
Pin Name
OE
LE
D7-D0
O7-O0
GND
V
CC
Description
Output Enable Input (Active LOW)
Latch Enable Input (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Note:
1. H = High Voltage Level, X = Don't Care,
L = Low Voltage Level, Z = High Impedance
1
PS2063A 01/15/97
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT573
3.3V 8-BIT TRANSPARENT LATCH
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................. –65°C to +150°C
Ambient Temperature with Power Applied ............................ –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ...... –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) .. –0.5V to +7.0V
DC Input Voltage .................................................................... –0.5V to +7.0V
DC Output Current .............................................................................. 120 mA
Power Dissipation .................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 2.7V to 3.6V)
Parameters
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Description
Input HIGH Voltage (Input pins)
Input HIGH Voltage (I/O pins)
Input LOW Voltage
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Min.
2.2
2.0
–0.5
Typ
(2)
—
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3.0
3.0
—
—
0.2
0.3
–85
—
150
Max.
5.5
5.5
0.8
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
—
0.2
0.4
0.5
–240
±100
—
Units
V
V
V
µA
µA
µA
µA
µA
µA
V
mA
mA
V
V
V
V
V
V
mA
µA
mV
V
OL
Output LOW Voltage
I
OS
I
OFF
V
H
Short Circuit Current
(4)
Power Down Disable
Input Hysteresis
V
CC
= Max.
V
IN
= 5.5V
—
V
CC
= Max.
V
IN
= V
CC
—
V
CC
= Max.
V
IN
= GND
—
V
CC
= Max.
V
IN
= GND
—
V
CC
= Max.
V
OUT
= 5.5V
—
V
CC
= Max.
V
OUT
= GND
—
V
CC
= Min., I
IN
= –18 mA
—
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
–36
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
50
V
CC
= Min.
I
OH
= –0.1 mA Vcc-0.2
V
IN
= V
IH
or V
IL
I
OH
= –3 mA
2.4
V
CC
= 3.0V,
I
OH
= –8 mA
2.4
(5)
V
IN
= V
IH
or V
IL
I
OH
= –24 mA
2.0
V
CC
= Min.
I
OL
= 0.1 mA
—
V
IN
= V
IH
or V
IL
I
OL
= 16 mA
—
I
OL
= 24 mA
—
(3)
V
CC
= Max. , V
OUT
= GND
–60
V
CC
= 0V, V
IN
or V
OUT
≤
4.5V
—
—
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
– 0.6V at rated current.
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Units
pF
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
2
PS2063A 01/15/97
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT573
3.3V 8-BIT TRANSPARENT LATCH
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
(4)
Test Conditions
(1)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
OE = GND
One Bit Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
I
= 10 MH
Z
50% Duty Cycle
OE = GND
One Bit Toggling
V
CC
= Max.,
Outputs Open
f
I
= 2.5 MH
Z
50% Duty Cycle
OE = GND
8 Bits Toggling
V
IN
= GND or V
CC
V
IN
= V
CC
– 0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
Typ
(2)
0.1
2.0
50
Max.
10
30
75
Units
µA
µA
µA/
MHz
1
2
3
4
5
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
– 0.6V
V
IN
= GND
0.6
2.3
mA
V
IN
= V
CC
– 0.6V
V
IN
= GND
2.1
4.7
(5)
6
7
8
9
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
10
11
12
13
14
15
3
PS2063A 01/15/97
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT573
3.3V 8-BIT TRANSPARENT LATCH
Switching Characteristics over Operating Range
(1)
LPT573
Com.
Parameters
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Description
Propagation Delay
Dx to Ox
Propagation Delay
LE to Ox
Output Enable Time
OE to Ox
Output Disable Time
(4)
OE to Ox
Setup Time HIGH
or LOW, Dx to LE
Hold Time HIGH
or LOW, Dx to LE
LE Pulse Width
(4)
HIGH
Output Skew
(5)
Conditions
(2)
C
L
= 50pF
R
L
= 500Ω
Min.
3)
1.5
2.0
1.5
1.5
2.0
1.5
6.0
0.5
Max.
8.0
12.0
9.5
6.5
1.5
2.0
1.5
1.5
2.0
1.5
5.0
0.5
LPT573A
Com.
Min.
(3)
Max.
5.2
8.5
6.5
5.5
1.5
2.0
1.5
1.5
2.0
1.5
5.0
0.5
LPT573C
Com.
Min.
(3)
Max.
4.2
5.5
5.5
5.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V,
extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction.
This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
4
PS2063A 01/15/97
京公网安备 11010802033920号
EEWORLD
