Am29LV2562M
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
26494
Revision
B
Amendment
+1
Issue Date
October 9, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am29LV2562M
512 Megabit (16 M x 32-Bit/32 M x 16-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Single power supply operation
— 3 volt read, erase, and program operations
■
VersatileI/O control
— Device generates data output voltages and tolerates
data input voltages on the CE# and DQ inputs/outputs
as determined by the voltage on the V
IO
pin; operates
from 1.65 to 3.6 V
TM
— 4-doubleword/8-word page read buffer
— 16-doubleword/32-word write buffer
■
Low power consumption (typical values at 3.0 V, 5
MHz)
— 26 mA typical active read current
— 100 mA typical erase/program current
— 2 µA typical standby mode current
■
Package options
— 80-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Group Unprotect: V
ID
-level method
of changing code in locked sector groups
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
■
Manufactured on 0.23 µm MirrorBit process
technology
TM
■
SecSi™ (Secured Silicon) Sector region
— 128-doubleword/256-word sector for permanent,
secure identification through an
8-doubleword/16-word random Electronic Serial
Number, accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
■
Flexible sector architecture
— Five hundred twelve 32 Kdoubleword (64 Kword)
sectors
■
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■
100,000 erase cycles per sector
■
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■
High performance
— 120 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 15 µs typical write buffer doubleword programming
time: 16-doubleword/32-word write buffer reduces
overall programming time for multiple-word updates
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
26494
Rev:
B
Amendment/+1
Issue Date:
October 9, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV2562M consists of two 256 Mbit, 3.0 volt
single power supply flash memory devices and is or-
ganized as 16,777,216 doublewords or 33,554,432
words. The device has a 32-bit wide data bus that can
also function as an 16-bit wide data bus by using the
WORD# input. The device can be programmed either
in the host system or in standard EPROM program-
mers.
An access time of 120 ns is available. Note that each
access time has a specific operating voltage range
(V
CC
) as specified in the
Product Selector Guide
and
the
Ordering Information
sections. The device is of-
fered in an 80-ball Fortified BGA package. Each de-
vice has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(WP#/ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14
(toggle)
status bits
or monitor the
Ready/Busy#
(RY/BY#)
outputs to determine whether the operation
is complete. To facilitate programming, an
Unlock By-
pass
mode reduces command sequence overhead by
requiring only two write cycles to program data instead
of four.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
IO
pin.
Refer to the Ordering Information section for valid V
IO
options.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups
of memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The
Program Sus-
pend/Program Resume
feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power cons umption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi™ (Secured Silicon) Sector
provides a
128-doubleword/256-word area for code or data that
can be permanently protected. Once this sector is pro-
tected, no further changes within the sector can occur.
The
Write Protect (WP#/ACC)
feature protects the
first or last sector by asserting a logic low on the WP#
pin.
AMD MirrorBit
TM
flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
www.amd.com
→
Flash Memory
→
Product Informa-
tion
→
MirrorBit
→
Flash Information
→
Technical Docu-
mentation.
The following is a partial list of documents
closely related to this product:
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
2
Am29LV2562M
October 9, 2003
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Special Package Handling Instructions .................................... 6
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
x16 Mode .................................................................................. 7
x32 Mode .................................................................................. 7
Table 1. Device Bus Operations ....................................................... 9
Chip Erase Command Sequence ........................................... 38
Sector Erase Command Sequence ........................................ 38
Figure 7. Erase Operation .............................................................. 39
Erase Suspend/Erase Resume Commands ........................... 39
DQ7 and DQ5: Data# Polling .................................................. 43
Figure 7. Data# Polling Algorithm .................................................. 43
DQ6 and DQ14: Toggle Bits I ................................................. 44
Figure 8. Toggle Bit Algorithm ........................................................ 45
VersatileIO (V
IO
) Control ........................................................ 9
Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................10
TM
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10
DQ2 and DQ10: Toggle Bits II ................................................ 45
Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10 ............ 45
DQ5 and DQ13: Exceeded Timing Limits ............................... 46
DQ3 and DQ11: Sector Erase Timer ...................................... 46
DQ1: Write-to-Buffer Abort ..................................................... 47
Table 12. Write Operation Status................................................... 47
Figure 9. Maximum Negative Overshoot Waveform ..................... 48
Figure 10. Maximum Positive Overshoot Waveform ..................... 48
Figure 11. Test Setup ..................................................................... 50
Table 13. Test Specifications ......................................................... 50
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12
Table 3. Autoselect Codes, (High Voltage Method) ....................... 23
Key to Switching Waveforms. . . . . . . . . . . . . . . . 50
Figure 12. Input Waveforms and
Measurement Levels ...................................................................... 50
Sector Group Protection and Unprotection ............................. 24
Table 4. Sector Group Protection/Unprotection Address Table ..... 24
Temporary Sector Group Unprotect ....................................... 26
Figure 1. Temporary Sector Group Unprotect Operation ................26
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...27
Read-Only Operations ........................................................... 51
Figure 13. Read Operation Timings ............................................... 51
Figure 14. Page Read Timings ...................................................... 52
SecSi (Secured Silicon) Sector Flash Memory Region .......... 28
Table 5. SecSi Sector Contents ...................................................... 28
Figure 3. SecSi Sector Protect Verify ..............................................29
Hardware Reset (RESET#) .................................................... 53
Figure 15. Reset Timings ............................................................... 53
Erase and Program Operations .............................................. 54
Figure 16. Program Operation Timings .......................................... 55
Figure 17. Accelerated Program Timing Diagram .......................... 55
Figure 18. Chip/Sector Erase Operation Timings .......................... 56
Figure 19. Data# Polling Timings (During Embedded Algorithms) . 57
Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 58
Figure 21. DQ2 vs. DQ6 ................................................................. 58
Hardware Data Protection ...................................................... 29
Low VCC Write Inhibit .....................................................................29
Write Pulse “Glitch” Protection ........................................................29
Logical Inhibit ..................................................................................29
Power-Up Write Inhibit ....................................................................29
Common Flash Memory Interface (CFI) . . . . . . . 29
Reading Array Data ................................................................ 33
Reset Command ..................................................................... 33
Autoselect Command Sequence ............................................ 33
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 34
Doubleword/Word Program Command Sequence ................. 34
Unlock Bypass Command Sequence ..............................................34
Write Buffer Programming ...............................................................34
Accelerated Program ......................................................................35
Figure 4. Write Buffer Programming Operation ...............................36
Figure 5. Program Operation ..........................................................37
Temporary Sector Unprotect .................................................. 59
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 59
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 60
Alternate CE# Controlled Erase and Program Operations ..... 61
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .......................................................................... 62
Program Suspend/Program Resume Command Sequence ... 37
Figure 6. Program Suspend/Program Resume ...............................38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 62
Erase And Programming Performance. . . . . . . . 63
TSOP Pin and BGA Package Capacitance . . . . . 63
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSC080–80-Ball Fortified Ball Grid Array
18 x 12 mm Package .............................................................. 64
October 9, 2003
Am29LV2562M
3
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