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IS61LV25616AL-10TLI-TR

Description
SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin TSOP-II T/R
Categorystorage    storage   
File Size287KB,16 Pages
ManufacturerISSI(Integrated Silicon Solution Inc.)
Websitehttp://www.issi.com/
Environmental Compliance
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IS61LV25616AL-10TLI-TR Overview

SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin TSOP-II T/R

IS61LV25616AL-10TLI-TR Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)3A991.b.2.a
Part StatusUnconfirmed
HTS8542.32.00.41
Chip Density (bit)4M
Number of Words256K
Number of Bits/Word (bit)16
Data Rate ArchitectureSDR
Address Bus Width (bit)18
Number of Ports1
Timing TypeAsynchronous
Max. Access Time (ns)10
Process TechnologyCMOS
Minimum Operating Supply Voltage (V)3.135
Typical Operating Supply Voltage (V)3.3
Maximum Operating Supply Voltage (V)3.6
Operating Current (mA)110
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)85
Supplier Temperature GradeIndustrial
PackagingTape and Reel
Supplier PackageTSOP-II
Pin Count44
Standard Package NameSOP
MountingSurface Mount
Package Height1.05(Max)
Package Length18.52(Max)
Package Width10.29(Max)
PCB changed44
Lead ShapeGull-wing
IS61LV25616AL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time:
— 10, 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 m
A
(typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
DECEMBER 2011
static RAM organized as 262,144 words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV25616AL is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP
and 48-pin Mini BGA (8mm x 10mm).
DESCRIPTION
The
ISSI
IS61LV25616AL is a high-speed, 4,194,304-bit
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
12/15/2011
1

IS61LV25616AL-10TLI-TR Related Products

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Description SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin TSOP-II T/R SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin SOJ SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 48-Pin Mini-BGA T/R SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin SOJ SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin LQFP T/R SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 44-Pin TSOP-II SRAM Chip Async Single 3.3V 4M-bit 256K x 16 10ns 48-Pin Mini-BGA
EU restricts the use of certain hazardous substances Compliant Not Compliant Compliant - - Compliant Compliant
ECCN (US) 3A991.b.2.a 3A991.b.2.a 3A991.b.2.a - - EAR99 EAR99
Part Status Unconfirmed Unconfirmed Active - - Unconfirmed Active
HTS 8542.32.00.41 8542.32.00.41 8542.32.00.41 - - 8542.32.00.41 8542.32.00.41
Chip Density (bit) 4M 4M 4M - - 4M 4M
Number of Words 256K 256K 256K - - 256K 256K
Number of Bits/Word (bit) 16 16 16 - - 16 16
Data Rate Architecture SDR SDR SDR - - SDR SDR
Address Bus Width (bit) 18 18 18 - - 18 18
Number of Ports 1 1 1 - - 1 1
Timing Type Asynchronous Asynchronous Asynchronous - - Asynchronous Asynchronous
Max. Access Time (ns) 10 10 10 - - 10 10
Process Technology CMOS CMOS CMOS - - CMOS CMOS
Minimum Operating Supply Voltage (V) 3.135 3.135 3.135 - - 3.135 3.135
Typical Operating Supply Voltage (V) 3.3 3.3 3.3 - - 3.3 3.3
Maximum Operating Supply Voltage (V) 3.6 3.6 3.6 - - 3.6 3.6
Operating Current (mA) 110 110 110 - - 110 110
Minimum Operating Temperature (°C) -40 -40 -40 - - -40 -40
Maximum Operating Temperature (°C) 85 85 85 - - 85 85
Supplier Temperature Grade Industrial Industrial Industrial - - Industrial Industrial
Supplier Package TSOP-II SOJ Mini-BGA - - TSOP-II Mini-BGA
Pin Count 44 44 48 - - 44 48
Standard Package Name SOP SOJ BGA - - SOP BGA
Mounting Surface Mount Surface Mount Surface Mount - - Surface Mount Surface Mount
Package Height 1.05(Max) 3.75(Max) - 0.64(Min) 0.6(Min) - - 1.05(Max) 0.6(Min)
Package Length 18.52(Max) 28.7(Max) 10 - - 18.52(Max) 10
Package Width 10.29(Max) 10.29(Max) 8 - - 10.29(Max) 8
PCB changed 44 44 48 - - 44 48
Lead Shape Gull-wing J-Lead Ball - - Gull-wing Ball

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