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ZL30363GDG2PROG

Description
Clock Generators & Support Products CC Plus ROM ZL30363 AAA WE Production
Categorysemiconductor    Analog mixed-signal IC   
File Size420KB,5 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
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ZL30363GDG2PROG Overview

Clock Generators & Support Products CC Plus ROM ZL30363 AAA WE Production

ZL30363GDG2PROG Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerMicrosemi
Product CategoryClock Generators & Support Products
TypeClock Synchronizers
Maximum Input Frequency750 MHz
Max Output Freq750 MHz
Number of Outputs16 Output
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Mounting StyleSMD/SMT
Package / CaseLBGA-144
PackagingBulk
Output TypeLVCMOS, LVPECL
ProductClock Generators
Jitter0.63 ps
Factory Pack Quantity160
ZL30363
IEEE 1588 and Synchronous Ethernet Packet
Clock Network Synchronizer
Short Form Data Sheet
Features
Two independent clock channels
Frequency and Phase Sync over Packet Networks
Frequency accuracy performance for WCDMA-
FDD, GSM, LTE-FDD and femtocell applications
Frequency performance for ITU-T G.823 and
G.824 synchronization interface, as well as
G.8261 PNT PEC and CES interfaces
Phase Synchronization performance for
WCDMA-TDD, Mobile WiMAX, TD-SCDMA and
CDMA2000 applications
Client holdover and reference switching
between multiple Servers
ITU-T G.8262 for SyncE EEC option 1 and 2
ITU-T G.813 for SONET/SDH SEC option 1 and
2
Telcordia GR-1244 and GR-253 Stratum 3 and
SMC
Support for G.781 SETS
Ordering Information:
ZL30363GDG2
144 Pin LBGA
Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Package size: 13 x 13 mm
May 2013
Trays
Any input clock rate from 1 Hz to 750 MHz
Automatic hitless reference switching and digital
holdover on reference fail
Flexible two-stage architecture to support
conversion between SONET/SDH and OTN rates
Digital PLLs with programmable bandwidth from
0.1 mHz up to 1 kHz
Programmable synthesizers
• Any output clock rate from 1 Hz to 750 MHz
with maximum jitter below 0.63 ps RMS
Operates from a single crystal resonator or clock
oscillator
Configurable via SPI/I
2
C interface
Physical Layer Equipment Clocks Synchronization
Osci
Osco
Ref0
Ref1
Ref2
Ref3
Ref4
Ref5
Ref6
Ref7
Ref8
Ref9
Ref10
Master Clock
Diff / Single Ended
Fr
0
= Br
0
*Kr
0
*Mr
0
/Nr
0
Diff / Single Ended
Fr
1
= Br
1
*Kr
1
*Mr
1
/Nr
1
Diff / Single Ended
Fr
2
= Br
2
*Kr
2
*Mr
2
/Nr
2
Diff / Single Ended
Fr
3
= Br
3
*Kr
3
*Mr
3
/Nr
3
Diff / Single Ended
Fr
4
= Br
4
*Kr
4
*Mr
4
/Nr
4
Diff / Single Ended
Fr
5
= Br
5
*Kr
5
*Mr
5
/Nr
5
Diff / Single Ended
Fr
6
= Br
6
*Kr
6
*Mr
6
/Nr
6
Diff / Single Ended
Fr
7
= Br
7
*Kr
7
*Mr
7
/Nr
7
Diff / Single Ended
Fr
8
= Br
8
*Kr
8
*Mr
8
/Nr
8
Single Ended
Fr
9
= Br
9
*Kr
9
*Mr
9
/Nr
9
Single Ended
Fr
10
= Br
10
*Kr
10
*Mr
10
/Nr
10
JTAG
Reference Monitors
State
Machine
ZL30363
Clock Generator 0
Synthesizer 0
Fs= Bs
0
*Ks
0
*16*Ms
0
/Ns
0
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff0_p/n
hpdiff1_p/n
hpoutclk0
hpoutclk1
Clock Generator 1
Synthesizer 1
Fs= Bs
1
*Ks
1
*16*Ms
1
/Ns
1
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff2_p/n
hpdiff3_p/n
hpoutclk2
hpoutclk3
DPLL0/NCO0
Select Loop band.,
Phase slope limit
DPLL1/NCO1
Select Loop band.,
Phase slope limit
Clock Generator 2
Synthesizer 2
Fs= Bs
2
*Ks
2
*16*Ms
2
/Ns
2
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff4_p/n
hpdiff5_p/n
hpoutclk4
hpoutclk5
Clock Generator 3
Configuration
and Status
Synthesizer 3
Fs= Bs
3
*Ks
3
*16*Ms
3
/Ns
3
Div A
Div B
Div C
Div D
LVPECL
LVPECL
LVCMOS
LVCMOS
hpdiff6_p/n
hpdiff7_p/n
hpoutclk6
hpoutclk7
JTAG
pwr_b
GPIO
SPI / I
2
C
Figure 1 - Functional Block Diagram
1
Copyright 2013, Microsemi Corporation. All Rights Reserved.

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Description Clock Generators & Support Products CC Plus ROM ZL30363 AAA WE Production Clock Generators & Support Products
Product Attribute Attribute Value Attribute Value
Manufacturer Microsemi Microsemi
Product Category Clock Generators & Support Products Clock Generators & Support Products
Packaging Bulk Tray
Factory Pack Quantity 160 160
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