Storage Temperature Range ............................ -65°C to +160°C
Lead Temperature (Soldering, 10s) ................................... 300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
V
CC
= full operating range, V
BATT
= 2.8V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
BATTERY BACKUP SWITCHING
Operating Voltage Range
(MAX690, MAX691, MAX694, MAX695 V
CC
)
Operating Voltage Range (MAX690, MAX691,
MAX694, MAX695 V
BATT
)
Operating Voltage Range
(MAX692, MAX693 V
CC
)
Operating Voltage Range
(MAX692, MAX693 V
BATT
)
V
OUT
Output Voltage
I
OUT
= 1mA
I
OUT
= 50mA
I
OUT
= 250µA, V
CC
< V
BATT
- 0.2V
I
OUT
= 1mA
I
OUT
= 50mA
V
CC
= 0V, V
BATT
= 2.8V
5.5V > V
CC
>
V
BATT
+ 1V
Power-up
Power-down
T
A
= +25°C
T
A
= full operating
range
-0.1
-1.0
70
50
4.75
2.0
4.5
2.0
V
CC
-
0.3
V
CC
-
0.5
V
BATT
- 0.1
V
CC
-
0.1
V
CC
-
0.25
V
BATT
- 0.02
2
3.5
0.6
5
10
1
+0.02
+0.02
µA
5.5
4.25
V
5.5
4.0
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
OUT
in Battery Backup Mode
Supply Current (Excluded I
OUT
)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, - = Charge)
Battery Switchover Threshold
(V
CC
- V
BATT
)
V
mA
µA
mV
www.maximintegrated.com
Maxim Integrated │ 2
MAX690–MAX695
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
V
CC
= full operating range, V
BATT
= 2.8V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short-Circuit Current
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Timeout Delay (MAX690/MAX691/
MAX692/MAX693)
Reset Timeout Delay (MAX694/MAX695)
Watchdog Timeout Period, Internal Oscillator
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET
and
LOW LINE
Output Voltage
RESET and
WDO
Output Voltage
Output Short-Circuit Current
WDI Input Threshold Logic-Low
WDI Input Threshold Logic-High
WDI Input Current
POWER-FAIL DETECTOR
PFI Threshold
PFI Current
PFO
Output Voltage
PFO
Short Circuit Source Current
I
SINK
= 3.2mA
I
SOURCE
= 1µA
PFI = V
IH
,
PFO
= 0V
3.5
1
3
25
V
CC
= 5V, T
A
= full
1.2
1.3
±0.01
1.4
±25
0.4
V
nA
V
V
µA
Figure 6, OSC SEL HIGH, V
CC
= 5V
Figure 6, OSC SEL HIGH, V
CC
= 5V
Long period, V
CC
= 5V
Short period, V
CC
= 5V
Long period
Short period
V
IL
= 0.4, V
IH
= 0.8V
CC
I
SINK
= 1.6mA, V
CC
= 4.25V
I
SOURCE
= 1µA, V
CC
= 5V
I
SINK
= 1.6mA
I
SOURCE
= 1µA, V
CC
= 5V
RESET,
RESET,
WDO, LOW LINE
V
CC
= 5V (Note 2)
V
CC
= 5V (Note 2)
WDI = V
OUT
WDI = 0V
-50
3.5
20
-15
50
3.5
1
3
25
0.8
3.5
0.4
35
140
1.0
70
3840
768
200
0.4
T
A
= full
operating range
MAX690, MAX691,
MAX694, MAX695
MAX692, MAX693
4.5
4.25
4.65
4.4
40
50
200
1.6
100
70
280
2.25
140
4097
1025
4.75
4.5
mV
ms
ms
s
ms
Clock
Cycles
ns
V
V
µA
V
µA
V
I
SINK
= 3.2mA
BATT ON = V
OUT
= 4.5V sink current
BATT ON = 0V source current
0.5
25
1
25
CONDITIONS
MIN
TYP
20
0.4
MAX
UNITS
mV
V
mA
µA
www.maximintegrated.com
Maxim Integrated │ 3
MAX690–MAX695
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
V
CC
= full operating range, V
BATT
= 2.8V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
CHIP ENABLE GATING
CE
IN Thresholds
CE
IN Pullup Current
I
SINK
= 3.2mA
CE
OUT Output Voltage
CE
Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Frequency
with External Capacitor
OSC SEL = 0V
OSC SEL = 0V
C
OSC
= 47pF
0
4
±2
5
250
µA
µA
kHz
kHz
I
SOURCE
= 3.0mA
I
SOURCE
= 1µA, V
CC
= 0V
V
CC
= 5V
V
OUT
- 1.5
V
OUT
- 0.05
50
200
ns
V
IL
V
IH
3.0
3
0.4
V
0.8
V
µA
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
The input voltage limits on PFI and WDI may be exceeded provided the input current is limited to less than 10mA.
Note 2:
WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and V
CC
is in the operating voltage range. WDI is
internally biased to 38% of V
CC
with an impedance of approximately 125kΩ.
Pin Description
PIN
MAX690/
MAX692/
MAX694
2
8
1
3
MAX691/
MAX693/
MAX695
3
1
2
4
NAME
FUNCTION
V
CC
V
BATT
V
OUT
GND
The +5V Input
Backup Battery Input. Connect to Ground if a backup battery is not used.
The higher of V
CC
or V
BATT
is internally switched to V
OUT
. Connect V
OUT
to V
CC
if
V
OUT
and V
BATT
are not used. Connect a 0.1µF or larger bypass capacitor to V
OUT
.
0V Ground Reference for All Signals
RESET
goes low whenever V
CC
falls below either the reset voltage threshold or the
V
BATT
input voltage. The reset threshold is typically 4.65V for the MAX690/691/694/695,
and 4.4V for the MAX692 and MAX693.
RESET
remains low for 50ms after V
CC
returns
to 5V, (except 200ms in MAX694/695).
RESET
also goes low for 50ms if the Watchdog
Timer is enabled but not serviced within its timeout period. The
RESET
pulse width can
be adjusted as shown in Table 1.
Watchdog Input (WDI). WDI is a three level input. If WDI remains either high or low for
longer than the watchdog timeout period,
RESET
pulses low and
WDO
goes low. The
Watchdog Timer is disabled when WDI is left floating or is driven to mid-supply. The
timer resets with each transition at the Watchdog Timer input.
Noninverting Input to the Power-Fail Comparator. When PFI is less than 1.3V,
PFO
goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
7
15
RESET
6
11
WDI
4
9
PFI
www.maximintegrated.com
Maxim Integrated │ 4
MAX690–MAX695
Microprocessor Supervisory Circuits
Pin Description (continued)
PIN
MAX690/
MAX692/
MAX694
5
—
—
MAX691/
MAX693/
MAX695
10
13
12
NAME
FUNCTION
PFO
CE
IN
CE
OUT
Output of the Power-Fail Comparator. It goes low when PFI is less than 1.3V. The
comparator is turned off and
PFO
goes low when V
CC
is below V
BATT
.
CE
Gating Circuit Input. Connect to GND or V
OUT
if not used.
CE
OUT goes low only when
CE
IN is low and V
CC
is above the reset threshold (4.65V
for MAX691 and MAX695, 4.4V for MAX693). See Figure 6.
BATT ON goes high when V
OUT
is internally switched to the V
BATT
input. It goes low
when V
OUT
is internally switched to V
CC
. The output typically sinks 25mA and can
directly drive the base of an external PNP transistor to increase the output current
above the 50mA rating of V
OUT
.
LOW LINE
goes low when V
CC
falls below the reset threshold. It returns high as soon
as V
CC
rises above the reset threshold. See Figure 6, Reset Timing.
Active-High Output. It is the inverse of
RESET.
When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time
delay and watchdog timeout period. When OSC SEL is low, the external oscillator input,
OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See Table 1.
When OSC SEL is low, OSC IN can be driven by an external clock to adjust both the
reset delay and the watchdog timeout period. The timing can also be adjusted by
connecting and external oscillator to this pin. See Figure 8. When OSC SEL is high or
floating, OSC IN selects between fast and slow Watchdog timeout periods.
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FPGA/CPLD
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