DS2223/DS2224
DS2223/DS2224
EconoRAM
FEATURES
PACKAGE OUTLINE
TO–92
•
Low–cost, general–purpose, 256–bit memory
– DS2223 has 256–bit SRAM
– DS2224 has 32–bit ROM, 224–bit SRAM
•
Reduces
single pin
control, address and data interface to a
•
Each DS2224 32–bit ROM is factory–lasered with a
unique serial number
•
DS2224 portion of ROM with custom code and unique
serial number available
SOT–223
1
1
2
3
•
Minimal
operating power: 45 nanocoulombs per
transaction @1.5V typical
•
Less than 15 nA standby current at 25°C
•
Nonvolatile data
1
2
3
2
BOTTOM VIEW
See Mech. Drawings
Section
4
3
retention easily achieved via low–
cost alkaline batteries or capacitors
lers
•
Directly connects to a port pin of popular microcontrol-
•
Operation from 1.2 to 5.5 volts
•
Popular TO–92 or SOT–223 surface mount package
•
Operates over industrial temperature range –40°C to
+85°C
TOP VIEW
See Mech. Drawings
Section
PIN CONNECTIONS
Pin 1
Pin 2
Pin 3
Pin 4
GND
DQ
V
CC
GND
–
–
–
–
Ground
Data In/Out
Supply
Ground
DESCRIPTION
The DS2223 and DS2224 EconoRAMs are fully static,
micro–powered, read/write memories in low–cost
TO–92 or SOT–223 packages. The DS2223 is orga-
nized as a serial 256 x 1 bit static read/write memory.
The DS2224’s first 32 bits are lasered with a unique ID
code at the time of manufacture; the remaining 224 bits
are static read/write memory. Signaling necessary for
reading or writing is reduced to just one interface lead.
Both the DS2223 and DS2224 are not recommended
for new designs. However, the parts will remain avail-
able until the year 2003, at least.
ORDERING INFORMATION
DS2223
DS2223Z
DS2223T
DS2223Y
DS2224
DS2224Z
DS2224T
DS2224Y
256–bit SRAM – TO–92 Package
256–bit SRAM – SOT–223 Package
1000 piece tape–and–reel of DS2223
2500 piece tape–and–reel of DS2223Z
32–bit serial number (ROM), 224–bit
SRAM – TO–92 Package
32–bit serial number (ROM), 224–bit
SRAM – SOT–223 Package
1000 piece tape–and–reel of DS2224
2500 piece tape–and–reel of DS2224Z
080598 1/10
DS2223/DS2224
OPERATION
All communications to and from the EconoRAM are
accomplished via a single interface lead. EconoRAM
data is read and written through the use of time slots. All
data is preceded by a command byte to specify the type
of transaction.
Once a specific transaction has been
initiated, either a read or a write, it must be com-
pleted for all memory locations before another
transaction can be started.
READ OR WRITE TRANSACTION
Read or write transactions are performed by initializing
the EconoRAM to a known state, issuing a command
byte, and then generating the time slots to either read
EconoRAM contents or write new data. Each transac-
tion consists of 264 time slots. Eight time slots transmit
the command byte, the remaining 256 time slots trans-
fer the data bits. (See Figure 5.) Once a transaction is
started, it must be completed before a new transaction
can begin.
To initially set the EconoRAM into a known state, 264
Write Zero time slots must be sent by the host. These
Write Zero time slots will not corrupt the data in the Eco-
noRAM since a command byte has not been written.
This operation will increment the address pointer inter-
nal to the EconoRAM to its maximum count value. Upon
reaching this maximum value, the EconoRAM will
ignore all additional Write Zero time slots issued to it and
the internal address pointer will remain locked at the top
count value. This condition is removed by the reception
of a Write One time slot, typically the first bit of a com-
mand byte.
Once the EconoRAM has been set into a known state,
the command byte is transmitted to the EconoRAM with
eight write time slots. This resets the address pointer
internal to the EconoRAM and prepares it for the
appropriate operation, either a read or a write.
After the command byte has been received by the Eco-
noRAM, the host controls the transfer of data. In the
case of a read transaction, the host issues 256 read time
slots. In the case of a write transaction, the host issues
256 write time slots according to the data to be written.
All data is read and written least significant bit first.
Although the DS2224 has the first 32 bits replaced by
lasered ROM rather than SRAM, it requires 256 write
time slots for a complete write transaction. The data
being sent during the first 32 write time slots has no
effect on the DS2224 other than advancing the internal
address pointer. As stated previously, it is not possible
to change from read to write or vice versa before a trans-
action is completed.
1–WIRE SIGNALLING
The EconoRAM requires strict protocols to insure data
integrity. The protocol consists of three types of signal-
ling on one line: Write 0 time slot, Write 1 time slot and
Read Data time slot. All these signals are initiated by the
host.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated
in Figures 1 through 3. All time slots are initiated by the
host driving the data line low. The falling edge of the data
line synchronizes the EconoRAM to the host by trigger-
ing a delay circuit in the EconoRAM. During write time
slots, the delay circuit determines when the EconoRAM
will sample the data line. For a read data time slot, if a “0”
is to be transmitted, the delay circuit determines how
long the EconoRAM will hold the data line low overriding
the 1 generated by the host. If the data bit is a “1”, the
EconoRAM will leave the read data time slot
unchanged.
COMMAND BYTE
The command byte to specify the type of transaction is
transmitted LSB first from the host to the EconoRAM
using write time slots. The first bit of the command byte
(see Figure 4) is a logic 1. This indicates to the Econo-
RAM that a command byte is being written. The next two
bits are the select bits which denote the physical
address of the EconoRAM that is to be accessed (set to
00 currently). The remaining five bits determine whether
a read or a write operation is to follow. If a write operation
is to be performed, all five bits are set to a logic 1 level. If
a read operation is to be performed, any or all of these
bits are set to a logic 0 level. All eight bits of the com-
mand byte are transmitted to the EconoRAM with a sep-
arate time slot for each bit.
080598 2/10
Embedded System
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