CS5124/6
CS5124/6
High Performance, Integrated Current Mode
PWM Controllers
Description
The CS5124/6 is a fixed frequency
current mode controller designed
specifically for DC-DC converters
found in the telecommunications
industry. The CS5124/6 integrates
many commonly required current
mode power supply features and
allows the power supply designer to
realize substantial cost and board
space savings. The product matrix is
as follows:
CS5124: 400kHz w/V
BIAS
Pin,
195mV first current sense threshold
CS5126: 200kHz w/SYNC Pin,
335mV first current sense threshold
The CS5124/6 integrates the follow-
ing features: Internal Oscillator, Slope
Compensation, Sleep On/Off, Under
Voltage Lock Out, Thermal
Shutdown, Soft Start Timer, Low
Voltage Current Sense for Resistive
Sensing, Second Current Threshold
for Pulse by Pulse Over Current
Protection, a Direct Optocoupler
Interface and Leading Edge Current
Blanking.
The CS5124/6 has supply range of
7.7V to 20V and is available in 8 pin
SO narrow package.
Features
s
Line UVLO Monitoring
s
Low Current Sense
Voltage for Resistive
Current Sensing
s
External Synchronization
to Higher or Lower
Frequency Oscillator
(CS5126 Only)
s
Bias for Start up Circuitry
(CS5124 Only)
s
Thermal Shutdown
s
Sleep On/Off Pin
s
Soft Start Timer
s
Leading Edge Blanking
s
Direct Optocoupler
Interface
s
90ns Propagation Delay
Applications Diagram
s
35ns Driver Rise and Fall
Times
s
Sleep Mode
D1
36-75VIN
L1
10µH
R2
200k
C2
1.5µF,
100V
R1
510k
Q1
ZVN3310A
R4
10Ω
R5
17.4k
CTX15-14514
T1
5VOUT
MBRD360CT
D4
R3
47Ω
Q2
IRFR220
R8
0.39Ω
Package Options
8 Lead SO Narrow
CS5124
BAS16LT1
C1
0.1µF,
100V
C4
0.47µF,
25V
C3
.022µF
R6
1k
C6
R7
30.1k
C5
47µF,
10V
V
CC
BIAS
UVLO
1
Gnd
GATE
V
CC
BIAS
ENABLE
UVLO
SS
C7
0.1µF
Gnd
GATE
IS
U2
I
SENSE
V
FB
.01µF
CS5124
C9
1000pF
SS
C8
1000pF
V
FB
TPS5908
R9
10.0k
ISOLATED
RTN
CS5126
V
CC
UVLO
SYNC
1
Gnd
GATE
48VRTN
I
SENSE
V
FB
48V to 5V, 1A flyback converter using the CS5124
SS
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 3/12/99
1
A
®
Company
CS5124/6
Absolute Maximum Ratings
Pin Symbol
Lead Name
V
MAX
20V
20V
20V
6V
6V
6V
6V
0V
20V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
0V
-0.3V
I
SOURCE
1mA
1mA
1mA
1mA
1mA
3mA
1mA
1.5A peak
200mA DC
1.5A Peak
200mA DC
I
SINK
1.5A Peak
200mA DC
1mA
1mA
1mA
2mA
20mA
1mA
1mA
1.5A Peak
200mA DC
V
CC
SYNC (CS5126)
V
BIAS
(CS5124)
UVLO
SS
V
FB
I
SENSE
GROUND
GATE
V
CC
Power Input
Clock Synchronization Input
V
CC
Clamp Output
UVLO Shutdown Input
Soft Start Capacitor Input
Voltage Feed Back Input
Current Sense Input
Ground
Gate Drive Output
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to 135°C
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to 150°C
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
ESD (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak
Electrical Characteristics: -40°C
≤
T
J
≤
125°C, -40°C
≤
T
A
≤
105°C, 7.60V
≤
V
CC
≤
20V, UVLO = 3.0V, I
SENSE
= 0V,
C
V(CC)
= 0.33µF, C
GATE
= 1nF (ESR = 10Ω), C
SS
= 470pF C
V(FB)
= 100pF
,
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
General
I
CC
Operating - V
GATE
not switching.
I
CC
at V
CC
Low
I
CC
Sleep
s
Low V
CC
Lockout
V
CC
Turn-on Threshold Voltage
V
CC
Turn-off Threshold Voltage
V
CC
Hysteresis
s
UVLO
Sleep Threshold Voltage
Sleep Threshold Voltage
Sleep Hysteresis
UVLO Turn-off
Threshold Voltage
UVLO Turn-on
Threshold Voltage
UVLO Hysteresis
UVLO Hysteresis
UVLO Input Bias Current
UVLO Clamp
V
CC
= 6V
V
UVL
= 1V
10
500
210
13
750
275
mA
µA
µA
7.2
6.8
350
7.7
7.3
425
8.3
7.8
500
V
V
mV
UVLO decreasing
UVLO increasing
(Note 1)
(Note 1)
Turn-on – Turnoff (-40°C
≤
T
J
≤
100°C)
(Note 1)
Turn-on – Turnoff (100°C
≤
T
J
≤
125°C)
(Note 1)
With UVLO sinking 1mA.
1.5
35
2.3
2.50
170
50
-1
5
1.8
1.88
85
2.45
2.63
185
185
2.3
2.45
150
2.6
2.76
200
400
1
12
V
V
mV
V
V
mV
mV
µA
V
7.5
2
CS5124/6
Electrical Characteristics: -40°C
≤
T
J
≤
125°C, -40°C
≤
T
A
≤
105°C, 7.60V
≤
V
CC
≤
20V, UVLO = 3.0V, I
SENSE
= 0V,
C
V(CC)
= 0.33µF, C
GATE
= 1nF (ESR = 10Ω), C
SS
= 470pF C
V(FB)
= 100pF
,
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
V
CC
Clamp and BIAS Pin
V
CC
Clamp Voltage
BIAS Minimum Voltage
BIAS Clamp
s
200kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
CS5124 Only. Connect an NFET as follows: BIAS = G, V
CC
= S, V
IN
= D.
36V
≤
V
IN
≤
60V, 220nF
≤
C
SS
≤
500nF, R = 500k
Measure Voltage on BIAS with:
10V
≤
V
CC
≤
20V and 50µA
≤
I
BIAS
≤
1mA
With BIAS pin sinking 1mA
CS5126 Only
175
78
12
200
82.5
18
225
85
23
kHz
%
mV/µs
7.275
1.6
12
7.9
2.8
15
8.625
4
20
V
V
V
Slope Compensation
(Normal operation)
Slope Compensation
(Synchronized operation)
(Note 1)
SYNC Input Threshold Voltage
SYNC Input Impedance
Measured with SYNC = 1V &10V
s
400kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
Slope Compensation
s
Soft Start
Soft Start Charge Current
Soft Start Discharge Current
V
SS
Voltage when V
FB
Begins to Rise
V
FB
= 300mV
CS5124 Only
7
1
50
12
2
120
16
3
230
mV/µs
V
kΩ
360
80.0
15
400
82.5
21
440
85.0
26
kHz
%
mV/µs
7
0.5
1.40
4.7
200
10
10.0
1.62
4.9
275
13
1.80
µA
mA
V
V
mV
Peak Soft Start Charge Voltage
Valley Soft Start Discharge Voltage
s
Current Sense
CS5124 Only
First Current Sense Threshold
At max duty cycle.
Second Current Sense Threshold
I
SENSE
to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
s
Current Sense
First Current Sense Threshold
Second Current Sense
Threshold
I
SENSE
to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
0 to 700mV pulse into I
SENSE
(after blanking time)
0 to 400mV pulse into I
SENSE
(Note 1)
CS5126 Only
At max duty cycle
400
170
250
60
90
195
275
90
130
60
215
315
130
180
mV
mV
ns
ns
mV
300
485
60
110
335
525
90
175
125
360
575
130
210
mV
mV
ns
ns
mV
0 to 800mV pulse into I
SENSE
(after blanking time)
0 to 550mV pulse into I
SENSE
(Note 1)
3
CS5124/6
Electrical Characteristics: -40°C
≤
T
J
≤
125°C, -40°C
≤
T
A
≤
105°C, 7.60V
≤
V
CC
≤
20V, UVLO = 3.0V, I
SENSE
= 0V,
C
V(CC)
= 0.33µF, C
GATE
= 1nF (ESR = 10Ω), C
SS
= 470pF C
V(FB)
= 100pF
,
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Voltage Feedback
V
FB
Pull-up Res.
V
FB
Clamp Voltage
V
FB
Clamp Voltage
V
FB
Fault Voltage Threshold
s
Output Gate Drive
Maximum Sleep
Pull-down Voltage
GATE High (AC)
GATE Low (AC)
GATE High Clamp Voltage
Rise Time
Fall Time
CS5124 Only
CS5126 Only
2.9
2.63
2.40
460
4.3
2.90
2.65
490
8.1
3.15
2.90
520
kΩ
V
V
mV
V
CC
= 6.0V, I
OUT
= 1mA
Series resistance < 1Ω (Note 1)
Series resistance < 1Ω (Note 1)
V
CC
= 20V
Measure GATE rise time,
1V < GATE < 9V; V
CC
=12V
Measure GATE fall time,
9V > GATE > 1V; V
CC
= 12V
V
CC
-1
11.0
1.2
V
CC
-0.5
0.0
13.5
45
25
2.0
V
V
0.5
16.0
65
55
V
V
ns
ns
s
Thermal Shutdown
Thermal Shutdown Temperature (Note 1) (GATE low)
Thermal Enable Temperature
(Note 1) (GATE switching)
Thermal Hysteresis
(Note 1)
Notes
1. Not tested in production. Specification is guaranteed by design.
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
135
100
15
150
125
25
165
150
35
°C
°C
°C
8 Lead SO Narrow
CS5124
1
2
CS5126
1
-
V
CC
BIAS
V
CC
Power Input Pin.
V
CC
Clamp Output Pin. This pin will control the gate of an N-channel MOS-
FET that in turn regulates V
CC
. This pin is internally clamped at 15V when
the IC is in sleep mode.
Clock Synchronization Pin. A positive edge will terminate the current PWM
cycle. Ground this pin when it is not used.
Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the
chip to "wake up" however the GATE remains low. A voltage greater than
2.6V on this pin allows the output to switch.
Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is
charged with 10µA and discharged with 10mA. The Soft Start capacitor con-
trols both soft-start time and hiccup mode frequency.
Voltage Feedback Pin. The collector of an optocoupler is typically tied to this
pin. This pin is pulled up internally by a 4.3kΩ resistor to 5V and is clamped
internally at 2.9V(2.65V). If V
FB
is pulled > 4V, the oscillator is disabled and
GATE will stay high. If the V
FB
pin is pulled < 0.49V, GATE will stay low.
Current Sense Pin. This pin is connected to the current sense resistor on the
primary side. If V
FB
is floating, the GATE will go low if I
SENSE
= 195mV
(335mV). If I
SENSE
> 275mV (525mV), Soft Start will be initiated.
Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally
clamped to 13.5V.
Ground Pin.
4
-
3
3
2
SYNC
UVLO
4
4
SS
5
5
V
FB
6
6
I
SENSE
7
8
7
8
GATE
Gnd
CS5124/6
Block Diagram
{CS5126 ONLY}
SYNC
V
CC
UVLO COMP
V
CC
OSC
DIS
G2
ENABLE
F3
R
F1
DRIVER
Q
V
CC
+
+
-
V
7.7 V/7.275V
V
REF
= 5V
Q
G1
S
R
GATE
RAMP
S
V5
REF
RESET DOMAIN
{85 mV/us}
170mV us
G7
G3
V5
REF
4500Ω
V
REFOK
LINE UVLO COMP
V
+
V5
REF
10µA
TSHUT
150°C/125°C
+
V
2.62 V/2.45V
V
FB
COMP
UVLO
+
-
BIAS
(CS5124 ONLY)
V
1.91 V/1.83V
+
SOFT START LATCH
F2
V
CC
2.9 R
G5
-
2ND I
COMP
+
V
{525mV}
275mV
BLANKING
BLANK
G6
S
R
Q
{2.65V}
2.90V
+
V
2.0V
V
+
R
SS COMP
275mV
V
SS
Powering the IC
V
CC
can be powered directly from a regulated supply
and requires 500µA of start-up current. The CS5124/6
includes a line bias pin (BIAS) that can be used to control a
series pass transistor for operation over a wide input volt-
age. The BIAS pin will control the gate voltage of an N-
channel MOSFET placed between V
IN
and V
CC
to regulate
V
CC
at 8V.
V
CC
and UVLO Pins
The UVLO pin has three different modes; low power shut-
down, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that V
IN
, as shown in
the application schematic, is ramped up starting at 0V with
the UVLO pin open. The SS and I
SENSE
pins also start at 0V.
While the UVLO is below 1.8V, the IC will remain in a low
current sleep mode and the BIAS pin of the CS5124 is inter-
nally clamped to a maximum of 15V. When the voltage on
the UVLO pin rises to between 1.8V and 2.6V the reference
for the V
CC
UVLO is enabled and V
CC
is regulated to 8V by
the BIAS pin (CS5124 only), but the IC remains in a UVLO
state and the output driver does not switch. When the
UVLO pin exceeds 2.6V and the V
CC
pin exceeds 7.7V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the I
SENSE
and V
FB
pins. The Soft Start capacitor begins charging from 0V at
5
+
-
+
-
LINE AMP
SET DOMAIN
V5
REF
+
-
SS AMP
+
1.32V
+
V
Theory of Operation
10µA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the V
FB
pin and the V
FB
volt-
age begins to rise. As V
FB
rises the duty cycle increases
until the supply comes into regulation.
Soft Start
Soft Start is accomplished by clamping the V
FB
pin 1.32V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124/6 starts, the Soft
Start capacitor is charged from a 10µA source from 0V to
4.9V. The V
FB
pin follows the Soft Start pin offset by –1.32V
until the supply comes into regulation or until the Soft
Start error amp is clamped at 2.9V (2.65V for the CS5126).
During fault conditions the Soft Start capacitor is dis-
charged at 10mA.
Fault Conditions
The CS5124/6 recognizes the following faults: UVLO off,
Thermal Shutdown, V
REF(OK)
, and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft Start capacitor. Soft Start will begin
only after all faults have been removed and the Soft Start
capacitor has been discharged to less than 0.275V. Each
fault will be explained in the following sections.
+
-
REMOTE
(SLEEP) COMP
+
PWM COMP
+
{125mV}
60mV
+
-
+
-
+
-
+
V
490mV
{1/5}
1/10
÷
V
V
FB
1000Ω
I
SENSE
Gnd
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