PRELIMINARY
CM3202
DDR V
DDQ
and Termination Voltage Regulator
Features
•
Two linear regulators
-Maximum 2A current from V
DDQ
-Source and sink up to 2A V
TT
current
1.7V to 2.8V adjustable V
DDQ
output voltage
500mV typical V
DDQ
dropout voltage at 2A
V
TT
tracking at 50% of V
DDQ
Excellent load and line regulation, low noise
Fast transient response
Meet JEDEC DDR-I and DDR-II memory power spec.
Linear regulator design requires no inductors and has
low external component count
Integrated power MOSFETs
Dual purpose ADJ/Shutdown pin
Built-in over-current limit with short-circuit foldback and
thermal shutdown for V
DDQ
and V
TT
Fast transient response
5mA quiescent current
TDFN-8 and SOIC-8 packages for high performance
thermal dissipation and easy PC board layout
Optional RoHS Compliant Lead-free packaging
Product Description
T
he CM3202 is a dual-output low noise linear regulator
•
•
•
•
•
•
•
•
•
•
•
•
•
•
designed to meet SSTL-2 and SSTL-3 specifications
for DDR-SDRAM V
DDQ
supply and termination voltage
V
TT
supply. With integrated power MOSFET’s, the
CM3202 can source up to 2A of V
DDQ
current, and
source or sink up to 2A V
TT
current. The typical drop-
out voltage for V
DDQ
is 500 mV at 2A load current.
The CM3202 provides fast response to transient load
changes. Load regulation is excellent, less than 1%,
from no load to full load. It also has built-in over-current
limits and thermal shutdown at 170°C.
The CM3202 is packaged in an easy-to-use TDFN-8
and SOIC-8. Low thermal resistance (55°C/W) allows it
to withstand 1.55W
(1)
dissipation at 85°C ambient. It
can operate over the industrial ambient temperature
range of –40°C to 85°C.
Note
(1)
:
If TDFN-8 is mounted on a double-sided printed circuit board with
two square inches of copper area, it can to withstand 2W dissipation
at 85°C ambient then.
Applications
•
•
•
•
•
•
•
•
DDR memory and active termination buses
Desktop Computers, Servers
Residential and Enterprise Gateways
DSL Modems
Routers and Switchers
DVD recorders
3D AGP cards
LCD TV and STB
Typical Application
3.3V
220u
4.7u
220u
4.7u
VDDQ
VDDQ
1
2
3
4
4.7u
VIN
VIN
VTT
GND
VDDQ
VDDQ
8
7
887
6
5
S/D
VTT
845
C hip
S et
DL0
RT0
DLn
RTn
CM3202
ADJSD
GND
220u
REF
Memory
DDR
1.25V , 2.5A
1k
V
REF
1u
©
2006 California Micro Devices Corp. All rights reserved.
05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
1
PRELIMINARY
CM3202
Package Pinout
PACKAGE / PINOUT DIAGRAM
TOP VIEW
8 7 6 5
TOP VIEW
V
DDQ
V
DDQ
ADJSD
GND
1 2 3 4
Pin 1
Marking
V
IN
V
IN
V
TT
GND
1
2
3
4
8
7
6
5
V
IN
NC
V
TT
NC
1
2
3
4
GND
PAD
8
7
6
5
V
DDQ
ADJSD
GND
GND
8-Lead SOIC Package
CM3202-00DE
Note: This drawing is not to scale.
8-Lead TDFN Package
CM3202-00SM
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish
Pins
8
8
Package
TDFN
SOIC
Ordering Part Number
1
CM3202-00DE
CM3202-00SM
Part Marking
CM3202
CM3202
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VIN to GND
Pin Voltages
V
DDQ
,V
TT
to GND
ADJSD to GND
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10s)
RATING
[GND - 0.3] to +6.0
[GND - 0.3] to +6.0
[GND - 0.3] to +6.0
-65 to +150
-40 to +85
300
UNITS
V
V
V
°C
°C
°C
©
2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
05/08/06
PRELIMINARY
CM3202
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
V
IN
= 3.3V, typical values are at T
A
= 25°C (unless otherwise specified)
SYMBOL
VIN
V
IN
V
UVLO
I
Q
Supply Voltage Range
Under-voltage Lockout
UVLO Hysterisis
Quiescent Current
All outputs are no load
V
DDQ
= 0V, V
TT
= 0V,
ADJSD = 3.3V (shutdown)
V
DDQ
= 2.5V, V
TT
= 1.25V, (no load)
V
OUT
= 2.5V
1.235
VADJSD = V
REF
I
O
= 10mA to 2A
V
IN
= 3.15V to 3.5V, I
O
= 10mA
V
IN
= 3.15V, I
O
= 2A
V
OUT
= 1.25V
V
OUT
= 1.25V
I
O
= 0A to 2A
I
O
= 0A to -2A
Over Temperature Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
3
3.3
2.5
200
200
5
2.8
1.250
30
1
1
500
2.8
2.8
1
1
170
50
1.265
200
3.6
V
V
mV
mA
mA
A
V
nA
%
%
mV
A
A
%
%
°C
°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
S
V
DDQ
Regulator
Output Current Limit
V
REF
I
BIAS
V
R LOAD
V
R LINE
V
DROPOUT
V
TT
Regulator
Output Current Limit (Source)
Output Current Limit (Sink)
V
R VTTLOAD
Load Regulation
Reference Voltage
Input Bias Current (I
ADJ
)
Load Regulation
Line Regulation
Dropout Voltage
©
2006 California Micro Devices Corp. All rights reserved.
05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
3
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
