DATASHEET
ISL6563
Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers
The ISL6563 two-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. Multiphase power conversion is a marked
departure from single phase converter configurations
employed to satisfy the increasing current demands of
modern microprocessors and other electronic circuits. By
distributing the power and load current, implementation of
multiphase converters utilize smaller and lower cost
transistors with fewer input and output capacitors. These
reductions accrue from the higher effective conversion
frequency with higher frequency ripple current due to the
phase interleaving process of this topology.
Outstanding features of this controller IC include
programmable VID codes compatible with Intel VRM9,
VRM10, as well as AMD’s Hammer microprocessors, along
with a system regulation accuracy of
1%.
The droop
characteristic, used to reduce the overshoot or undershoot of
the output voltage, is easily programmed with a single resistor.
Important features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the microprocessor. Like other Intersil multiphase
controllers, the ISL6563 uses cost and space-saving
r
DS(ON)
sensing for channel current balance, dynamic
voltage positioning, and overcurrent protection. Channel
current balancing is automatic and accurate with the
integrated current-balance control system. Overcurrent
protection can be tailored to any application with no need for
additional parts. These features provide advanced protection
for the microprocessor and power system.
FN9126
Rev 8.00
Jun 10, 2010
Features
• Integrated Two-Phase Power Conversion
• Both 5V and 12V Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses r
DS(ON)
• Precision Output Voltage Regulation
-
1%
System Accuracy Over-Temperature (Commercial)
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD’s
Hammer DAC codes
- Resistor-Programmable Droop Voltage
• Fast Transient Recovery Time
• Overcurrent Protection
• Improved, Multi-tiered Overvoltage Protection
• Capable of Start-up into a Pre-Charged Output
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
• Pb-Free (RoHS Compliant)
Pinout
ISL6563
(24 LD QFN)
TOP VIEW
UGATE1
19
18 PHASE1
17 LGATE1
25
GND
16 PVCC
15 LGATE2
14 PGND
13 PHASE2
7
ISEN
8
VCC
9
OFS
10
SSEND
11
BOOT2
12
UGATE2
BOOT1
20
ENLL
21
VID2
VID3
23
VID4
22
Ordering Information
PART NUMBER
(Note 2)
ISL6563CRZ
TEMP.
RANGE
PART
(°C)
MARKING
65 63CRZ
PACKAGE
(Pb-free)
PKG.
DWG. #
0 to +70 24 Ld 4x4 QFN L24.4x4B
0 to +70 24 Ld 4x4 QFN L24.4x4B
0 to +70 24 Ld 4x4 QFN L24.4x4B
-40 to +85 24 Ld 4x4 QFN L24.4x4B
-40 to +85 24 Ld 4x4 QFN L24.4x4B
VID0
DACSEL/VID5
VRM10
COMP
FB
2
3
4
5
6
VID1
1
24
ISL6563CRZ-T (Note 1) 65 63CRZ
ISL6563CRZ-TK (Note 1) 65 63CRZ
ISL6563IRZ
ISL6563IRZ-T (Note 1)
ISL6563EVAL1
NOTES:
65 63IRZ
65 63IRZ
Evaluation Platform
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free
material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9126 Rev 8.00
Jun 10, 2010
Page 1 of 20
ISL6563
Absolute Maximum Ratings
Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . -0.3V to +6.25V
Absolute Boot Voltage, V
BOOT
. . . . . PGND - 0.3V to PGND + 27V
Phase Voltage, V
PHASE
. . . . . . . . . . V
BOOT
- 7V to V
BOOT
+ 0.3V
Upper Gate Voltage, V
UGATE
. . . . V
PHASE
- 0.3V to V
BOOT
+ 0.3V
Lower Gate Voltage, V
LGATE
. . . . . . . . PGND - 0.3V to VCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . HBM Class 1 JEDEC STD
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
QFN Package (Notes 3, 4). . . . . . . . . .
43
7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Test Conditions: V
CC
= 5V, T
J
= 0°C to +85°C, Unless Otherwise Specified.
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
VCC POR (Power-On Reset) Threshold
I
VCC
; ENLL = high
VCC Rising
VCC Falling
PVCC POR (Power-On Reset) Threshold
PVCC Rising
PVCC Falling
Switching Frequency (per Channel)
(Note 5)
Oscillator Ramp Amplitude (Note 6)
Maximum Duty Cycle (Note 6)
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Hysteresis (Note 6)
COMP Shutdown Threshold
COMP Shutdown Maximum Pull-Down Impedance
REFERENCE AND DAC
System Accuracy
T
J
= -40°C to +85°C
DAC Input Low Voltage
DAC Input High Voltage
DAC Input Pull-Up Current
ERROR AMPLIFIER
DC Gain (Note 5)
Gain-Bandwidth Product (Note 6)
Slew Rate (Note 6)
Maximum Output Voltage
Minimum Output Voltage
R
L
= 10k to ground
C
L
= 100pF, R
L
= 10k to ground
C
L
= 100pF, Load =
400µA
Load = 1mA
Load = -1mA
-
-
-
3.90
-
96
20
8
4.20
0.80
-
-
-
-
0.90
dB
MHz
V/µs
V
V
VIDx = 0V
-1
-1.5
-
0.8
-
-
-
-
-
45
1
1.5
0.4
-
-
%
%
V
V
µA
-
-
0.23
-
0.61
60
0.36
-
-
-
0.49
15
V
mV
V
T
J
= +25°C to +85°C
T
J
= -40°C
V
PP
-
4.2
3.7
-
-
189
166
-
-
4
4.4
3.9
4.2
3.3
222
205
1.33
66
6
4.6
4.1
-
-
255
241
-
-
mA
V
V
V
V
kHz
kHz
V
%
FN9126 Rev 8.00
Jun 10, 2010
Page 4 of 20
ISL6563
Electrical Specifications
PARAMETER
OVERCURRENT PROTECTION
Overcurrent Trip Level
PROTECTION
Overvoltage Threshold while IC Disabled
VRM9.0 configuration
Hammer and VRM10.0 configurations
Overvoltage Threshold
Overvoltage Hysteresis
SWITCHING TIME
UGATE Rise Time (Note 6)
LGATE Rise Time (Note 6)
UGATE Fall Time (Note 6)
LGATE Fall Time (Note 6)
UGATE Turn-On Non-overlap (Note 6)
LGATE Turn-On Non-overlap (Note 6)
OUTPUT
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
NOTES:
5. Parameter magnitude at T
J
= -40°C determined through characterization.
6. Limits should be considered typical and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
100mA Source Current
100mA Sink Current
100mA Source Current
100mA Sink Current
-
-
-
-
0.5
0.4
0.5
0.3
1.3
1.0
1.3
1.0
t
RUGATE;
V
VCC
= 5V, 3nF Load
t
RLGATE;
V
VCC
= 5V, 3nF Load
t
FUGATE;
V
VCC
= 5V, 3nF Load
t
FLGATE;
V
VCC
= 5V, 3nF Load
t
PDHUGATE
; V
VCC
= 5V, 3nF Load
t
PDHLGATE
; V
VCC
= 5V, 3nF Load
-
-
-
-
-
-
8
8
8
4
8
8
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
FB Rising
1.90
1.60
-
-
1.95
1.65
VID +200mV
100
2.00
1.70
-
-
V
V
V
mV
-
95
-
µA
Test Conditions: V
CC
= 5V, T
J
= 0°C to +85°C, Unless Otherwise Specified.
(Continued)
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
Timing Diagram
t
PDHUGATE
t
RUGATE
t
FUGATE
UGATE
LGATE
t
FLGATE
t
PDHLGATE
t
RLGATE
FN9126 Rev 8.00
Jun 10, 2010
Page 5 of 20
京公网安备 11010802033920号
EEWORLD
