A54SX32A-CQ256M datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> A54SX32A-CQ256M

A54SX32A-CQ256M: DescriptionFPGA - Field Programmable Gate Array SXA; CategoryProgrammable logic devices Programmable logic; File Size407KB，51 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

A54SX32A-CQ256M Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	A54SX32A-CQ256M	-	-	View	Buy Now

A54SX32A-CQ256M Overview

FPGA - Field Programmable Gate Array SXA

A54SX32A-CQ256M Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	QFF,
Contacts	256
Reach Compliance Code	compliant
Other features	IT CAN ALSO OPERATE WITH 3.3V AND 5V
maximum clock frequency	217 MHz
Combined latency of CLB-Max	1.4 ns
JESD-30 code	S-CQFP-F256
JESD-609 code	e0
length	36 mm
Configurable number of logic blocks	1800
Equivalent number of gates	48000
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1800 CLBS, 48000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.3 mm
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	36 mm
Base Number Matches	1

Preview

Download Datasheet

View All

v2.0

HiRel SX-A Family FPGAs

Features and Benefits

Leading Edge Performance

•

215 MHz System Performance (Military Temperature)

5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)

240 MHz Internal Performance (Military Temperature)

•

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and Design

Theft

Cold-Sparing Capability

Individual Output Slew Rate Control

QML Certified Devices

100% Military Temperature Tested (–55°C to +125°C)

33 MHz PCI Compliant

CPLD and FPGA Integration

Single-Chip Solution

Configurable I/O Support for 3.3 V/5 V PCI, LVTTL,

and TTL

Configurable Weak Resistor Pull-Up or Pull-Down for

Tristated Outputs during Power-Up

Up to 100% Resource Utilization and 100% Pin

Locking

2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Very Low Power Consumption

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary-Scan Testing in Compliance with IEEE

1149.1 (JTAG)

A54SX32A

32,000

48,000

2,880

1,800

1,080

1,980

228

Yes

5.3 ns

0 ns

Std, –1

84, 208, 256

A54SX72A

72,000

108,000

6,036

4,024

2,012

4,024

213

Yes

6.7 ns

0 ns

Std, –1

208, 256

Specifications

•

48,000 to 108,000 Available System Gates

Up to 228 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

0.25/0.22 µ CMOS Process Technology

Features

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (no sequencing required

for supply voltages)

Class B Level Devices

Three Standard Hermetic Package Options

•

Product Profile

Device

Capacity

Typical Gates

System Gates

Logic Modules

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

Maximum User I/Os

Global Clocks

Quadrant Clocks

Boundary-Scan Testing

3.3 V / 5 V PCI

Clock-to-Out

Input Set-Up (External)

Speed Grades

Package (by Pin Count)

CQFP

N o ve m b e r 2 0 0 6

See the Actel website for the latest version of the datasheet.

HiRel SX-A Family FPGAs

Table of Contents

General Description

QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

HiRel SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Detailed Specifications

2.5 V/3.3 V/5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

5 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

3.3 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

HiRel SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Package Pin Assignments

84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

International Traffic in Arms Regulations (ITAR) and Export Administration

Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

v 2 .0

Recommended Resources

Recording and playback circuit with Dolby noise reduction function and detection method

TDA2822D power amplifier circuit diagram

Thyristor medium frequency power supply control and protection circuit

Using ammonium button to control motor start and stop circuit diagram

Wireless remote control doorbell circuit diagram

Micro waiting power square wave generating circuit

How to crack Protel 99 SE in Windows 7: 1: First find the windows folder in the system disk. 2: Open the windows folder, find the package source program ADVPCB99SE, and open the ADVPCB99SE program. 3: Add package library... Change the dark ...; 769936811 PCB Design

Could you help me analyze the reason? Thanks!: I am so worried. The interrupt programs of ADC12 and Time_A run normally. When I add the separately debugged serial program, I still cannot receive complete data. Sometimes even the sampling and outpu...; 自由女神 Microcontroller MCU

Usage of the FSRAMPERCENT parameter in CONFIG.BIB: [p=26, null, left][color=#333333][font=Arial][size=14px]The specific settings can be found in Control Panel -> System -> Memory after the system starts. The default is to split the memory 50-50, half ...; gooogleman Linux and Android

Domestic chips recommend Unisplendour chips: Domestic chips recommend Unisplendour chips Model: SC9863A Official introduction: SC9863A is a highly integrated LTE smartphone platform that integrates an octa-core ARM Cortex-A55 processor, IMG8322 ...; 你好再见 Domestic Chip Exchange

How to control the number of PWM pulse outputs in STM32: How does STM32 control the number of PWM pulse outputs? I use PWM pulses as the synchronization clock for my peripherals, so I need exact values!...; loolen stm32/stm8

I saw a problem elsewhere and was quite interested. I came here to ask the experts about the occupancy problem in the configuration.: I have seen a problem elsewhere, but I don't know how to do it myself. I am quite interested in it, so I would like to ask an expert to configure a 512*24bit fifo and M4K RAM block. [img]file:///C:\Us...; 琉璃珠 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components