Blackfin
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see
Operating Conditions
on Page 23)
Qualified for Automotive Applications (see
Automotive Prod-
ucts on Page 66)
Programmable on-chip voltage regulator
182-ball and 208-ball CSP_BGA packages
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only)
Controller area network (CAN) 2.0B interface
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I
2
S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 32 interrupt inputs
Serial peripheral interface (SPI) compatible
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timer/counters with PWM support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), 8 with high current drivers
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
MEMORY
Up to 132K bytes of on-chip memory
Instruction SRAM/cache and instruction SRAM
Data SRAM/cache plus additional dedicated data SRAM
Scratchpad SRAM (see
Table 1 on Page 3
for available
memory configurations)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
WATCHDOG TIMER
B
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
RTC
INTERRUPT
CONTROLLER
CAN
TWI
SPORT0
DMA
CONTROLLER
DMA
EXTERNAL
BUS
PORT J
SPORT1
PPI
UART0-1
SPI
TIMER7-0
ETHERNET MAC
(See Table 1)
GPIO
PORT G
DMA CORE BUS
EXTERNAL ACCESS BUS
GPIO
PORT F
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
BOOT ROM
GPIO
PORT H
Figure 1. Functional Block Diagram
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Rev. J
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ADSP-BF534/ADSP-BF536/ADSP-BF537
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Peripherals ................................. 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Port ....................... 10
UART Ports ...................................................... 10
Controller Area Network (CAN) ............................ 11
TWI Controller Interface ...................................... 11
10/100 Ethernet MAC .......................................... 11
Ports ................................................................ 12
Parallel Peripheral Interface (PPI) ........................... 12
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 14
Clock Signals ..................................................... 15
Booting Modes ................................................... 16
Instruction Set Description .................................... 17
Development Tools .............................................. 17
Additional Information ........................................ 18
Related Signal Chains ........................................... 18
Pin Descriptions .................................................... 19
Specifications ........................................................ 23
Operating Conditions ........................................... 23
Electrical Characteristics ....................................... 25
Absolute Maximum Ratings ................................... 29
ESD Sensitivity ................................................... 29
Package Information ............................................ 29
Timing Specifications ........................................... 30
Output Drive Currents ......................................... 50
Test Conditions .................................................. 52
Thermal Characteristics ........................................ 56
182-Ball CSP_BGA Ball Assignment ........................... 57
208-Ball CSP_BGA Ball Assignment ........................... 60
Outline Dimensions ................................................ 63
Surface-Mount Design .......................................... 65
Automotive Products .............................................. 66
Ordering Guide ..................................................... 67
REVISION HISTORY
2/14—Rev. I to Rev. J
Corrected typographical error from Three 16-bit MACs to Two
16-bit MACs in
Features ............................................ 1
Updated
Development Tools .................................... 17
Added t
HDRE
parameter to
Serial Port Timing ................ 38
Added footnotes in
Serial Port Timing ........................ 38
Rev. J |
Page 2 of 68 |
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
GENERAL DESCRIPTION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are
members of the Blackfin
®
family of products, incorporating the
Analog Devices, Inc./Intel Micro Signal Architecture (MSA).
Blackfin processors combine a dual-MAC, state-of-the-art sig-
nal processing engine, the advantages of a clean, orthogonal
RISC-like microprocessor instruction set, and single-instruc-
tion, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are
completely code and pin compatible. They differ only with
respect to their performance, on-chip memory, and presence of
the Ethernet MAC module. Specific performance, memory, and
feature configurations are shown in
Table 1.
Table 1. Processor Comparison
ADSP-BF534
ADSP-BF536
ADSP-BF537
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The Blackfin processor is a highly integrated system-on-a-chip
solution for the next generation of embedded network-con-
nected applications. By combining industry-standard interfaces
with a high performance signal processing core, cost-effective
applications can be developed quickly, without the need for
costly external components. The system peripherals include an
IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only), a CAN 2.0B controller, a TWI controller,
two UART ports, an SPI port, two serial ports (SPORTs), nine
general-purpose 32-bit timers (eight with PWM capability), a
real-time clock, a watchdog timer, and a parallel peripheral
interface (PPI).
Features
Ethernet MAC
CAN
TWI
SPORTs
UARTs
SPI
GP Timers
Watchdog Timers
RTC
Parallel Peripheral Interface
GPIOs
L1 Instruction
SRAM/Cache
L1 Instruction
SRAM
Memory
L1 Data
Configuration SRAM/Cache
L1 Data SRAM
L1 Scratchpad
L3 Boot ROM
Maximum Speed Grade
Package Options:
CSP_BGA
CSP_BGA
—
1
1
2
2
1
8
1
1
1
48
16K bytes
48K bytes
32K bytes
32K bytes
4K bytes
2K bytes
500 MHz
208-Ball
182-Ball
1
1
1
2
2
1
8
1
1
1
48
16K bytes
1
1
1
2
2
1
8
1
1
1
48
16K bytes
BLACKFIN PROCESSOR PERIPHERALS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con-
tain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configura-
tion as well as excellent overall system performance (see
Figure 1).
The processors contain dedicated network communi-
cation modules and high speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power manage-
ment control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
All of the peripherals, except for the general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor’s various
memory spaces, including external SDRAM and asynchronous
memory. Multiple on-chip buses running at up to 133 MHz
provide enough bandwidth to keep the processor core running
along with activity on all of the on-chip and external
peripherals.
The Blackfin processors include an on-chip voltage regulator in
support of the processors’ dynamic power management capabil-
ity. The voltage regulator provides a range of core voltage levels
when supplied from V
DDEXT
. The voltage regulator can be
bypassed at the user’s discretion.
48K bytes 48K bytes
32K bytes 32K bytes
—
4K bytes
2K bytes
400 MHz
208-Ball
182-Ball
32K bytes
4K bytes
2K bytes
600 MHz
208-Ball
182-Ball
By integrating a rich set of industry-leading system peripherals
and memory, the Blackfin processors are the platform of choice
for next-generation applications that require RISC-like pro-
grammability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. J |
Page 3 of 68 |
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
BLACKFIN PROCESSOR CORE
As shown in
Figure 2,
the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates, and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1 32
DA0 32
TO MEMORY
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
RAB
32
PREG
SD 32
LD1 32
LD0 32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
32
32
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
BARREL
SHIFTER
40
A0
32
40
40
40
A1
8
16
8
8
16
ASTAT
SEQUENCER
ALIGN
8
DECODE
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. J |
Page 4 of 68 |
February 2014
ADSP-BF534/ADSP-BF536/ADSP-BF537
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have
three blocks of on-chip memory providing high-bandwidth
access to the core.
The first block is the L1 instruction memory, consisting of
64K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM, which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM, and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. A separate row can
be open for each SDRAM internal bank, and the SDRAM con-
troller supports up to 4 internal SDRAM banks, improving
overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
MEMORY ARCHITECTURE
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view
memory as a single unified 4G byte address space, using 32-bit
addresses. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of
this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide
a good cost/performance balance of some very fast, low latency
on-chip memory as cache or SRAM, and larger, lower cost, and
performance off-chip memory systems. (See
Figure 3).
The on-chip L1 memory system is the highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 516M bytes of
physical memory.
I/O Memory Space
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do
not define a separate I/O space. All resources are mapped
through the flat 32-bit address space. On-chip I/O devices have
their control registers mapped into memory-mapped registers
(MMRs) at addresses near the top of the 4G byte address space.
These are separated into two smaller blocks, one which contains
the control MMRs for all core functions, and the other which
contains the registers needed for setup and control of the on-
chip peripherals outside of the core. The MMRs are accessible
only in supervisor mode and appear as reserved space to on-
chip peripherals.
Booting
The Blackfin processor contains a small on-chip boot kernel,
which configures the appropriate peripheral for booting. If the
Blackfin processor is configured to boot from boot ROM
Rev. J |
Page 5 of 68 |
February 2014
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