Philips Semiconductors
Product specification
3.3V Octal bus transceiver/register (3-State)
74LVT646
FEATURES
•
Combines 74LVT245 and 74LVT574 type functions in one device
•
Independent registers for A and B buses
•
Multiplexed real–time and stored data
•
Output capability: +64mA/–32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
Live insertion/extraction permitted
•
No bus current loading when output is tied to 5V bus
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
Power-up 3-State
•
Power-up reset
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
resistors to hold unused inputs
DESCRIPTION
The LVT646 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device consists of bus transceiver circuits with 3-State outputs,
D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or the internal
registers.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes High.
Output Enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the
high impedance port may be stored in either the A or B register or
both.
The Select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE is active (Low).
In the isolation mode (OE = High), data from Bus A may be stored in
the B register and/or data from Bus B may be stored in the A
register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time. The examples on the
next page demonstrate the four fundamental bus management
functions that can be performed with the 74LVT646.
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 3.3V
V
I/O
= 0V or 3.0V
Outputs disabled; V
I/O
= 0V or 3.0V
Outputs disabled; V
CC
= 3.6V
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance
CP, S, OE, DIR
I/O capacitance
Total supply current
TYPICAL
2.8
2.7
4
10
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT646 D
74LVT646 DB
74LVT646 PW
NORTH AMERICA
74LVT646 D
74LVT646 DB
74LVT646PW DH
DWG NUMBER
SOT163-1
SOT399-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
CPAB /
CPBA
SAB / SBA
DIR
A0 – A7
B0 – B7
OE
GND
V
CC
FUNCTION
A to B clock input / B to A
clock input
A to B select input / B to
A select input
Direction control input
Data inputs/outputs (A
side)
Data inputs/outputs (B
side)
Output enable input
(active-low)
Ground (0V)
Positive supply voltage
1, 23
2, 22
3
4, 5, 6, 7, 8, 9, 10,
11
20, 19, 18, 17, 16,
15, 14, 13
21
12
24
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
A6 10
A7 11
GND 12
SV00045
1998 Feb 19
2
853-1747 18987
Philips Semiconductors
Product specification
3.3V Octal bus transceiver/register (3-State)
74LVT646
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A OR B
A
B
A
B
A
B
A
B
}
OE
L
DIR CPAB CPBA SAB SBA
L
X
X
X
L
OE
L
H
DIR CPAB CPBA SAB SBA
X
X
L
X
}
OE
L
L
H
H
L
X
DIR CPAB CPBA SAB SBA
↑
X
↑
X
↑
↑
X
X
X
X
X
X
}
OE
L
L
L
H
DIR CPAB CPBA SAB SBA
X
H or L
H or L
X
X
H
H
X
}
SV00049
FUNCTION TABLE
INPUTS
OE
X
X
H
H
L
L
L
L
H
L
X
↑
*
=
=
=
=
DIR
X
X
X
X
L
L
CPAB
↑
X
↑
H or L
X
X
CPBA
X
↑
↑
H or L
X
H or L
SAB
X
X
X
X
X
X
SBA
X
X
X
X
L
H
An
Input
Unspecified
output*
Input
Output
DATA I/O
Bn
Unspecified
output*
Input
Input
Input
OPERATING MODE
Store A, B unspecified
Store B, A unspecified
Store A and B data
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
H
X
X
L
X
Real time A data to B bus
Input
Output
H
H or L
X
H
X
Stored A data to B bus
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every Low-to-High transition of the clock.
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V Octal bus transceiver/register (3-State)
74LVT646
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
O
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%, f
≥
1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
MIN
2.7
0
2.0
0.8
–32
32
mA
64
10
+85
ns/V
°C
MAX
3.6
5.5
V
V
V
V
mA
UNIT
1998 Feb 19
5
FPGA/CPLD
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