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8T79S838-08NLGI8

Description
Clock Buffer 1 to 8 Differential 4 Bank 2 Pair Buffer
Categorysemiconductor    Analog mixed-signal IC   
File Size437KB,25 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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8T79S838-08NLGI8 Overview

Clock Buffer 1 to 8 Differential 4 Bank 2 Pair Buffer

8T79S838-08NLGI8 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology, Inc.)
Product CategoryClock Buffer
RoHSDetails
Number of Outputs8 Output
Maximum Input Frequency1.5 GHz
Propagation Delay - Max650 ps
Supply Voltage - Max3.465 V
Supply Voltage - Min2.375 V
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Mounting StyleSMD/SMT
Package / CaseVFQFPN-32
PackagingReel
Height1 mm
Input TypeLVDS, LVPECL
Length5 mm
Output TypeLVDS, LVPECL
Width5 mm
Duty Cycle - Max60 %
Max Output Freq1.5 GHz
Moisture SensitiveYes
Factory Pack Quantity6000
1-to-8 Differential to Universal Output
Fanout Buffer
IDT8T79S838-08I
DATA SHEET
General Description
The IDT8T79S838-08I is a high performance, 1-to-8, differential input
to universal output fanout buffer. The device is designed for signal
fanout of high-frequency clock signals in applications requiring output
frequencies generated simultaneously. The IDT8T79S838-08I is
optimized for 3.3V and 2.5V supply voltages and a temperature range
of -40°C to 85°C. The device is packaged in a space-saving 32 lead
VFQFN package.
Features
Four banks of two output pairs
Individual output type control, LVDS or LVPECL, via
serial interface
Individual outputs remain enabled while serial loading new
device configurations
One differential PCLK, nPCLK input
PCLK, nPCLK input pair can accept the following differential input
levels: LVPECL, LVDS levels
Maximum input frequency: 1.5GHz
LVCMOS control inputs
Individual output enable/disable control via serial interface
2.375V to 3.465V supply voltage operation
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
Pin Assignment
QBO
nQB0
nQB1
nQC0
QB1
QC0
QC1
nQC1
QA0
nQA0
VCC
24
23
22
21
20
19
18
V
CC
25
26
17
16
15
V
CC
V
EE
QD0
nQD0
QD1
nQD1
V
CC
PWR_SEL
PCLK
nPCLK
Pulldown
Pullup / Pulldown
QA1
nQA1
V
EE
nQA1
IDT8T79S838-08I
27
28
29
30
31
32
1
2
3
4
5
6
7
8
LE
14
QB0
nQB0
VEE
VEE
QA1
nQA0
QB1
nQB1
QA0
V
CC
32 lead VFQFN
5mm x 5mm x 0.925mm
Pad size 3.15mm x 3.15mm
NL package
Top View
13
12
11
10
9
QC0
nQC0
PWR_SEL
Pulldown
SDATA
SCLK
MISO
nPCLK
PCLK
VEE
QD0
nQD0
QD1
nQD1
OE
LE
SCLK
SDATA
Pulldown
Pulldown
Pulldown
Pulldown
Output Type and
Output Enable
logic
MISO
VEE VEE VEE VEE
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
1
©2014 Integrated Device Technology, Inc.
V
CC
OE
QC1
nQC1
nc
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