PI3V724
1 to 2 VGA Demux
Features
ÎÎ
Full VGA 1:2 demux with VSIS compliance
Description
Pericom’s PI3V724 is a 7-channel video mux/demux used to
switch between multiple VGA sources or end points. In a note-
book application where analog video signals are found in both
the notebook and the dock, a switch solution is required to switch
between the two video port locations. With the high bandwidth
of ~1.7GHz, the signal integrity will remain strong even through
the long FR4 trace between the notebook and the docking sta-
tion. In addition to high signal performance, the video signals are
also protected against high ESD with integrated diodes to VDD
and GND that will support up to +/-4kV contact ESD protection.
In addition to switching, the product also integrates a monitor
detection feature. The monitor detection feature works indepen-
dently on each of the two outputs and allows automatic switching
as well as a self generated HPD signal that lets the system know
when a monitor is connected or disconnected.
à
R, G, B, Hsync, Vsync, DDC data, and DDC clk
channels are switched
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Integrated monitor detection circuit allows Automatic or
manual control
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Generates hot plug output signal to inform system when
monitor is present or not
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Dual Power Supply, 3.3V and 5V
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Integrated DDC level shifter from 5V to 3.3V(bi-directional)
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Integrated 5V H/V output buffer with +/-24mA drive
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ESD tolerance on video I/O pins up to +/-4kV contact per
IEC61000-4-2 specification
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-3dB BW of 1.7GHz (typ)
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Low Xtalk, (-38dB typ)
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Low and Flat ON-STATE resistance (Ron = 4-Ohm,
Ron(Flat) = 0.5ohm, typ)
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Low input/output capacitance (Con = 5.6pF, typ)
ÎÎ
Packaging (Pb-free and Green):
à
32-contact TQFN (ZL)
Pin Diagram
GND
Priority/SEL
OUT
Test
R
G
GND
V
DD
B
H_SOURCE
V_SOURCE
MS
SDA_SOURCE
SCL_SOURCE
Rref
32 31 30 29 28
1
27
2
26
3
4
5
6
7
8
9
10
GND
25
24
23
22
21
20
19
18
CE
R1
R2
G1
G2
V
DD
B1
B2
H1_OUT
H2_OUT
V1_OUT
V2_OUT
11
17
12 13 14 15 16
SDA1
SDA2
SCL1
SCL2
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V
DD
5_IN
10/22/14
1 to 2 VGA Demux
Block Diagram
Result
detect
EN
Result
EN
V
V
V
V
PI3V724
B1
B
MS
Priority/SEL
CE
Rref
Logic
Control
Timer
pulse
+5V
V1
V
V
Detection Start Logic
V
V
V_SOURCE
Buffer
V2
G
R
H_SOURCE
SDA_SOURCE
SCL_SOURCE
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V
V
V
V
V
V
To timer
V
detect
B2
OUT
Buffer
G1
R1
G2
R2
+5V
H1_OUT
Buffer
Buffer
H2_OUT
Control
Logic
SDA1
5V to 3.3V
Level Shifter
SCL1
SDA2
SCL2
2
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10/22/14
1 to 2 VGA Demux
Pinout Table
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PI3V724
Name
R
G
GND
Vdd
B
H_Source
V_Source
MS
SDA_Source
SCL_Source
Rref
SDA1
SDA2
SCL1
SCL2
Vdd5_IN
V2_out
V1_out
H2_out
H1_out
B2
B1
Vdd
G2
G1
R2
R1
CE
Type
I/O
I/O
Ground
Power
I/O
I
I
I
I/O
I/O
I
I/O
I/O
I/O
I/O
I (Power)
O
O
O
O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I
Description
Red signal from source
Green signal from source
Ground
3.3V Power Supply
Blue signal from source
Horizontal Synchronous signal from source. Internal 300Kohm pull-down
Vertical Synchronous signal from source. Internal 300Kohm pull-down
Mode Select (switch between auto switch vs. manual switch). OUTx pins work
regardless of MS pin status. Internal pull down.
DDC data signal from source
DDC clock signal from source
Connect external resistor to ground to determine which application scheme
best matches your design. For actual R values, please see page 6
DDC data signal from VGA connector 1
DDC data signal from VGA connector 2
DDC clock signal from VGA connector 1
DDC clock signal from VGA connector 2
5V input power supply
Buffered, vertical synch signal output for VGA connector #2
Buffered vertical synchronous signal driving VGA connector #1
Buffered, horizontal synch signal output for VGA connector #2
Buffered horizontal synchronous signal driving VGA connector #1
Un-buffered, Blue signal driving VGA connector 2
Un-buffered, Blue signal driving VGA connector 1
3.3V Power Supply
Un-buffered, Green signal driving VGA connector 2
Un-buffered, Green signal driving VGA connector 1
Un-buffered, Red signal driving VGA connector 2
Un-buffered, Red signal driving VGA connector 1
Chip enable input. If signal is LOW, then chip is fully functional. If signal is
HIGH, then IC is powered down and all I/O’s are hi-z
open drain output describing external monitor status. If connected, OUT is
LOW, if not connected, OUT is hi-z. OUT will only provide the status of the
CHOSEN port.
Chosen port can be determined based on manual switching
or automatic switching (please see truth table for more information on how to
configure into auto mode or manual mode)
Output Port selection or output port priority depending on MS pin status
Ground
please tie high or leave floating for normal operation. internal pull-up
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29
OUT
O
30
31
32
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Priority/SEL
GND
Test
I
Ground
I
1 to 2 VGA Demux
Truth Table
CE/
0
0
0
0
1
PI3V724
MS (Internal
pull-down)
0
0
1
1
x
Switching
Mode
Automatic
Switching
Automatic
Switching
Pin 30 Role
Priority Pin
Priority Pin
SEL
N/A
N/A
0
1
x
Priority
0
1
N/A
N/A
x
Result
Port1 has priority
Port 2 has priority
Port 1 is active
Port 2 is active
all I/O's hi-z
Manual Switch-
SELpin
ing
Manual Switch-
SELpin
ing
N/A
N/A
Automatic switching scheme
As external monitors are properly detected, the PI3V724 can support automatic switching.
If only one monitor is connected, then the port is easily chosen regardless of what pin 30 (priority) pin status is.
Port selection (only one monitor is present)
At power on, MS pin (pin 31) is checked to determine if auto switching is enabled or not (to enable, MS needs to be LOW). Next the
part will look to see if external monitors are connected or not. If only one monitor is connected, the PI3V724 will automatically en-
able the signal path to drive the connected the monitor. OUT pin will then be pulled LOW.
Port selection (both monitors are present)
At power on, MS pin (pin 31) is checked to determine if auto switching is enabled or not (to enable, MS needs to be LOW). Next the
part will look to see if external monitors are connected or not. If only both monitors are connected, the PI3V724 will then check
the priority pin (pin 30). If pin 30 is LOW, then port 1 will have priority and therefore will be activated. However, if pin 30 is HIGH,
then port 2 will have priority and therefore port 2 will be enabled.
State Machine Reset Procedure
•
•
•
•
If the monitor from chosen port is disconnected, the state machine is reset (to determine chosen port, see above).
If MS pin status changes, state machine is reset
If CE/ pin goes high then low again, state machine is reset
If Vdd goes low and then high again, state machine resets
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1 to 2 VGA Demux
Application Note
Introduction
PI3V724 is a full VGA de-mux switch with integrated monitor detection circuit. Port switching can be selected manually or auto-
matically to offer more flexibility to users.
PI3V724
Automatic Monitor Detection
If MS pin (pin 8) is set to low or float, PI3V724 enters auto switch mode. When external monitor(s) is/are properly detected,
PI3V724 can support automatic switching.
Detection Pulse
When auto switch mode is selected via MS pin, PI3V724 sends a detection pulse through BLUE signal to check if any termination is
present. Once a monitor is attached, its termination is determined. PI3V724 will switch to the port with such termination accord-
ingly.
Result
detect
EN
Result
EN
V
V
V
V
B1
B
V
MS
Priority/SEL
CE
Rref
Logic
Control
Timer
pulse
V
V
Detection Start Logic
PI3V724 Detection Block Diagram
A detection pulse is sent by PI3V724 every 1.6 seconds when source or sink is not attached. Furthermore, the detection pulse is sent
immediately after sensing Vsync pulse. The detection pulse is of the width within 30us and the voltage level around 0.7V.
PI3V724 Detection Pulse on Blue B2 without Source or Sink Device
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V
V
V
V
V
V
detect
B2
5
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10/22/14
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