– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
•
Supports powerdown modes at the link level (L0, L0s, L1,
L2/L3 Ready and L3) and at the device level (D0, D3
hot
)
– Unused SerDes disabled
◆
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
◆
Thirty-two General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES48H12 provides
the most efficient system interconnect switching solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides 192 Gbps of aggregated,
full-duplex switching capacity through 48 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification 1.1.
The PES48H12 is based on a flexible and efficient layered architec-
ture. The PCI Express layers consist of SerDes, Physical, Data Link and
Transaction layers. The PES48H12 can operate either as a store and
forward switch or a cut-through switch and is designed to switch memory
and I/O transactions. It supports eight Traffic Classes (TCs) and two
Virtual Channels (VCs) with sophisticated resource management to
enable efficient switching and I/O connectivity.
SMBus Interface
The PES48H12 contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES48H12,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES48H12 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the SMBus
address to which the device responds to be configured. In the master
interface, these address pins allow the SMBus address of the serial
configuration EEPROM from which data is loaded to be configured. The
SMBus address is set up on negation of PERSTN by sampling the
corresponding address pins. When the pins are sampled, the resulting
address is assigned as shown in Table 1.
Non-bifurcated
x8
x8
Fully Bifurcated
x4
x4
x4
x4
3 2
x8
1 0
11
x8
10
2
1
0
4
5
6 7
x8
3
4
11
10
9
x4
x4
x4
x4
x4
8 9
x8
5
6
x4
7
x4
8
x4
Figure 2 Port Configuration Examples
Note:
The configurations in the above diagram show the maximum port widths. The PES48H12 can negotiate to narrower port widths —
x4, x2, or x1.
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October 3, 2011
IDT 89HPES48H12 Data Sheet
Bit
1
2
3
4
5
6
7
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES48H12 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES48H12 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES48H12 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES48H12 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
PES48H12
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES48H12
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES48H12 supports PCI Express Hot-Plug on each downstream port (ports 1 through 11). To reduce the number of pins required on the
device, the PES48H12 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following
reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12. In response to an I/O expander interrupt, the PES48H12 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES48H12 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
3 of 48
October 3, 2011
IDT 89HPES48H12 Data Sheet
Pin Description
The following tables lists the functions of the pins provided on the PES48H12. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ-
ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Signal
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1RN[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2RN[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3RN[3:0]
PE3TP[3:0]
PE3TN[3:0]
PE4RP[3:0]
PE4RN[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5RN[3:0]
PE5TP[3:0]
PE5TN[3:0]
PE6RP[3:0]
PE6RN[3:0]
PE6TP[3:0]
PE6TN[3:0]
PE7RP[3:0]
PE7RN[3:0]
Type
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive pairs for
port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive.
Differential PCI Express receive pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs
for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs
for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive pairs for
port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive pairs for
port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs
for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs
for lanes 4 through 7.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive pairs for
port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 4.
PCI Express Port 5 Serial Data Receive.
Differential PCI Express receive pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs
for lanes 4 through 7.
PCI Express Port 5 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs
for lanes 4 through 7.
PCI Express Port 6 Serial Data Receive.
Differential PCI Express receive pairs for
port 6.
PCI Express Port 6 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 6.
PCI Express Port 7 Serial Data Receive.
Differential PCI Express receive pairs for
port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs
for lanes 4 through 7.
Table 2 PCI Express Interface Pins (Part 1 of 2)
O
I
O
I
O
I
O
I
O
I
O
I
4 of 48
October 3, 2011
IDT 89HPES48H12 Data Sheet
Signal
PE7TP[3:0]
PE7TN[3:0]
PE8RP[3:0]
PE8RN[3:0]
PE8TP[3:0]
PE8TN[3:0]
PE9RP[3:0]
PE9RN[3:0]
PE9TP[3:0]
PE9TN[3:0]
PE10RP[3:0]
PE10RN[3:0]
PE10TP[3:0]
PE10TN[3:0]
PE11RP[3:0]
PE11RN[3:0]
PE11TP[3:0]
PE11TN[3:0]
REFCLKM
Type
O
Name/Description
PCI Express Port 7 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs
for lanes 4 through 7.
PCI Express Port 8 Serial Data Receive.
Differential PCI Express receive pairs for
port 8.
PCI Express Port 8 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 8.
PCI Express Port 9 Serial Data Receive.
Differential PCI Express receive pairs for
port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs
for lanes 4 through 7.
PCI Express Port 9 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs
for lanes 4 through 7.
PCI Express Port 10 Serial Data Receive.
Differential PCI Express receive pairs for
port 10.
PCI Express Port 10 Serial Data Transmit.
Differential PCI Express transmit pairs
for port 10.
PCI Express Port 11 Serial Data Receive.
Differential PCI Express receive pairs for
port 11. When port 10 is merged with port 11, these signals become port 10 receive
pairs for lanes 4 through 7.
PCI Express Port 11 Serial Data Transmit.
Differential PCI Express transmit pairs
for port 11. When port 10 is merged with port 11, these signals become port 10 trans-
mit pairs for lanes 4 through 7.
PCI Express Reference Clock Mode Select.
This signal selects the frequency of the
reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
PCI Express Reference Clock.
Differential reference clock pair input. This clock is
used as the reference clock by on-chip PLLs to generate the clocks required for the
system logic and on-chip SerDes. The frequency of the differential reference clock is
determined by the REFCLKM signal.
Table 2 PCI Express Interface Pins (Part 2 of 2)
I
O
I
O
I
O
I
O
I
REFCLKP[3:0]
REFCLKN[3:0]
I
Signal
MSMBADDR[4:1]
MSMBCLK
Type
I
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the serial
EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
Master SMBus Data.
This bidirectional signal is used for data on the master SMBus.
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