AS4C2M32SA-6TIN
AS4C2M32SA-6TCN
AS4C2M32SA-7TCN
Features
•
Fast access time:
5.4/5.4
ns
•
Fast Clock rate: 166/143 MHz
•
Fully synchronous operation
•
Internal pipelined architecture
•
Four internal banks (512K x 32bit x 4bank)
•
Programmable Mode
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst-Read-Single-Write
•
Burst stop function
•
Individual byte controlled by DQM0-3
•
Auto Refresh and Self Refresh
•
Operating Temperature:
- Commercial (0°C~+70
°
C)
- Industrial (-40°C~+85
°C)
•
4096 refresh cycles/64ms
•
Single +3.3V ± 0.3V power supply
•
Interface: LVTTL
Overview
The 64Mb SDRAM is a high-speed CMOS synchronous
DRAM containing 67,108,864bits. It is internally
configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 512K
x 32 bit banks is organized as 2048 rows by 256 columns
by 32 bits. Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a Bank Activate command which is then
followed by a Read or Write command.
The SDRAM provides for programmable Read or Write
burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. By
having a programmable mode register, the system can
choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth.
•
Package:
- 86-pin 400 x 875 mil plastic TSOP II package (Pb and Halogen Free)
Table
1.
Ordering Information
Product part No
AS4C2M32SA-6TIN
AS4C2M32SA-6TCN
AS4C2M32SA-7TCN
Org
2M x 32
2M x 32
2M x 32
Temperature
Industrial
-40°C
to
+85°C
Commercial
0°C to
+70°C
Commercial
0°C to
+70°C
Max Clock (MHz)
166 MHz
166 MHz
143 MHz
Package
86-pin TSOP II
86-pin TSOP II
86-pin TSOP II
Confidential
-2/54-
Rev.1.0
Sep. 2015
AS4C2M32SA-6TIN
AS4C2M32SA-6TCN
AS4C2M32SA-7TCN
Pin Descriptions
Symbol Type Description
CLK
CKE
Input
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Input
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low
synchronously with clock (set-up and hold time same as other inputs), the internal clock is
suspended from the next clock cycle and the state of output and burst address is frozen as long
as the CKE remains low. When all banks are in the idle state, deactivating the clock controls
the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the
device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during Power Down and
Self Refresh modes, providing low standby power.
Input
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. The bank address BA0 and BA1 is used latched in
mode register set.
Table
2.
Pin Details
BA0,
BA1
A0-A10 Input
Address Inputs:
A0-A10 are sampled during the BankActivate command (row address A0-
A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to
select one location out of the 512K available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The
address inputs also provide the op-code during a Mode Register Set or Special Mode Register
Set command.
CS#
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
Input
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction with
the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS#
are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the
Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BA is turned on to the active
state. When the WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Input
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction
with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is
held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS#
"LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."
Input
Write Enable:
The WE# signal defines the operation commands in conjunction with the RAS#
and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select
the BankActivate or Precharge command and Read or Write command.
RAS#
CAS#
WE#
DQM0 - Input
Data Input/Output Mask: Data Input Mask:
DQM0-DQM3 are byte specific. Input data is
DQM3
masked when DQM is sampled HIGH during a write cycle. DQM3 masks DQ31-DQ24, DQM2
masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
DQ0- Input/
Data I/O:
The DQ0-31 input and output data are synchronized with the positive edges of CLK.
DQ31 Output The I/Os are byte-maskable during Reads and Writes.
NC
V
DDQ
V
SSQ
V
DD
V
SS
Confidential
-
No Connect:
These pins should be left unconnected.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity.
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
Supply
Power Supply:
+3.3V±0.3V
Supply
Ground
-5/54-
Rev.1.0
Sep. 2015
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
