power, full binary-coded decimal (BCD) clock/calendar
plus 56 bytes of NV SRAM. Address and data are
2
transferred serially through an I C, bidirectional bus.
The clock/calendar provides seconds, minutes, hours,
day, date, month, and year information. The end of
the month date is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or 12-
hour format with AM/PM indicator. The DS1307 has a
built-in power-sense circuit that detects power failures
and automatically switches to the backup supply.
Timekeeping operation continues while the part
operates from the backup supply.
BENEFITS AND FEATURES
Completely Manages All Timekeeping Functions
o
Real-Time Clock Counts Seconds, Minutes,
Hours, Date of the Month, Month, Day of the
Week, and Year with Leap-Year
Compensation Valid Up to 2100
o
56-Byte, Battery-Backed, General-Purpose
RAM with Unlimited Writes
o
Programmable Square-Wave Output Signal
Simple Serial Port Interfaces to Most
Microcontrollers
2
o
I C Serial Interface
Low Power Operation Extends Battery Backup
Run Time
o
Consumes Less than 500nA in Battery-
Backup Mode with Oscillator Running
o
Automatic Power-Fail Detect and Switch
Circuitry
8-Pin DIP and 8-Pin SO Minimizes Required
Space
Optional Industrial Temperature Range: -40°C to
+85°C Supports Operation in a Wide Range of
Applications
Underwriters Laboratories® (UL) Recognized
TYPICAL OPERATING CIRCUIT
V
CC
V
CC
CRYSTAL
V
CC
R
PU
R
PU
X1
SCL
X2
V
CC
SQW/OUT
CPU
SDA
DS1307
V
BAT
GND
R
PU
= t
r
/C
b
PIN CONFIGURATIONS
TOP VLEW
X1
X2
V
BAT
GND
SO (150 mils)
V
CC
SQW/OUT
SCL
SDA
X1
X2
V
BAT
GND
PDIP (300 mils)
V
CC
SQW/OUT
SCL
SDA
ORDERING INFORMATION
PART
DS1307+
DS1307N+
DS1307Z+
DS1307ZN+
DS1307Z+T&R
DS1307ZN+T&R
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
VOLTAGE (V)
5.0
5.0
5.0
5.0
5.0
5.0
PIN-PACKAGE
8 PDIP (300 mils)
8 PDIP (300 mils)
8 SO (150 mils)
8 SO (150 mils)
8 SO (150 mils) Tape and Reel
8 SO (150 mils) Tape and Reel
TOP MARK*
DS1307
DS1307N
DS1307
DS1307N
DS1307
DS1307N
+Denotes
a lead-free/RoHS-compliant package.
*A
“+” anywhere on the top mark indicates a lead-free package. An “N” anywhere on the top mark indicates an industrial temperature range device.
Underwriters Laboratories, Inc. is a registered certification mark of Underwriters Laboratories, Inc.
1 of 14
REV: 3/15
DS1307 64 x 8, Serial, I C Real-Time Clock
2
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground .................................................................................... -0.5V to +7.0V
Operating Temperature Range (Noncondensing)
Commercial ................................................................................................................................ 0°C to +70°C
Industrial .................................................................................................................................. -40°C to +85°C
Storage Temperature Range ............................................................................................................. -55°C to +125°C
Soldering Temperature (DIP, leads) ........................................................................................ +260°C for 10 seconds
Soldering Temperature (surface mount)…..……………………….Refer to the JPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0°C to +70°C, T
A
= -40°C to +85°C.) (Notes 1, 2)
PARAMETER
Supply Voltage
Logic 1 Input
Logic 0 Input
V
BAT
Battery Voltage
SYMBOL
V
CC
V
IH
V
IL
V
BAT
CONDITIONS
MIN
4.5
2.2
-0.3
2.0
3
TYP
5.0
MAX
5.5
V
CC
+ 0.3
+0.8
3.5
UNITS
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V to 5.5V; T
A
= 0°C to +70°C, T
A
= -40°C to +85°C.) (Notes 1, 2)
PARAMETER
Input Leakage (SCL)
I/O Leakage (SDA, SQW/OUT)
Logic 0 Output (I
OL
= 5mA)
Active Supply Current
(f
SCL
= 100kHz)
Standby Current
V
BAT
Leakage Current
Power-Fail Voltage (V
BAT
= 3.0V)
SYMBOL
I
LI
I
LO
V
OL
I
CCA
I
CCS
I
BATLKG
V
PF
1.216 x
V
BAT
(Note 3)
5
1.25 x
V
BAT
CONDITIONS
MIN
-1
-1
TYP
MAX
1
1
0.4
1.5
200
50
1.284 x
V
BAT
UNITS
µA
µA
V
mA
µA
nA
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, V
BAT
= 3.0V; T
A
= 0°C to +70°C, T
A
= -40°C to +85°C.) (Notes 1, 2)
PARAMETER
V
BAT
Current (OSC ON);
SQW/OUT OFF
V
BAT
Current (OSC ON);
SQW/OUT ON (32kHz)
V
BAT
Data-Retention Current
(Oscillator Off)
SYMBOL
I
BAT1
I
BAT2
I
BATDR
CONDITIONS
MIN
TYP
300
480
10
MAX
500
800
100
UNITS
nA
nA
nA
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
2 of 14
DS1307 64 x 8, Serial, I C Real-Time Clock
2
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V to 5.5V; T
A
= 0°C to +70°C, T
A
= -40°C to +85°C.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
4.7
(Notes 5, 6)
(Note 4)
CONDITIONS
MIN
0
4.7
4.0
4.7
4.0
4.7
0
250
1000
300
TYP
MAX
100
UNITS
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
CAPACITANCE
(T
A
= +25°C)
PARAMETER
Pin Capacitance (SDA, SCL)
Capacitance Load for Each Bus
Line
SYMBOL
C
I/O
C
B
(Note 7)
CONDITIONS
MIN
TYP
MAX
10
400
UNITS
pF
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
All voltages are referenced to ground.
Limits at -40°C are guaranteed by design and are not production tested.
I
CCS
specified with V
CC
= 5.0V and SDA, SCL = 5.0V.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period (t
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